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Patch: sparc.md: Use define_constant.
- To: gcc-patches at gcc dot gnu dot org
- Subject: Patch: sparc.md: Use define_constant.
- From: RDBrown at mira dot net
- Date: Fri, 30 Mar 2001 22:35:39 +1000 (EST)
- Reply-To: RDBrown at mira dot net,RodneyBrown at mynd dot com
Based on 0320 snapshot. No regressions on sparc-sun-solaris-2.5.1 after
building at bootstrap4.
2001-03-30 Rodney Brown <RodneyBrown@mynd.com>
* config/sparc/sparc.md: Use define_constants for registers & unspecs.
--- gcc/config/sparc/sparc.md.orig Fri Mar 16 12:52:23 2001
+++ gcc/config/sparc/sparc.md Wed Mar 28 23:43:09 2001
@@ -24,34 +24,46 @@
;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
-;; Uses of UNSPEC and UNSPEC_VOLATILE in this file:
-;;
-;; UNSPEC: 0 movsi_{lo_sum,high}_pic
-;; pic_lo_sum_di
-;; pic_sethi_di
-;; 1 update_return
-;; 2 get_pc
-;; 5 movsi_{,lo_sum_,high_}pic_label_ref
-;; 6 seth44
-;; 7 setm44
-;; 8 setl44
-;; 9 sethh
-;; 10 setlm
-;; 11 embmedany_sethi, embmedany_brsum
-;; 13 embmedany_textuhi
-;; 14 embmedany_texthi
-;; 15 embmedany_textulo
-;; 16 embmedany_textlo
-;; 18 sethm
-;; 19 setlo
-;;
-;; UNSPEC_VOLATILE: 0 blockage
-;; 1 flush_register_windows
-;; 2 goto_handler_and_restore
-;; 3 goto_handler_and_restore_v9*
-;; 4 flush
-;; 5 do_builtin_setjmp_setup
-;;
+
+;; -------------------------------------------------------------------------
+;; Constants
+;; -------------------------------------------------------------------------
+
+(define_constants [
+ (SP_REG 14) ;; %sp
+ (O7_REG 15) ;; %o7
+ (I7_REG 31) ;; %i7
+ (F0_REG 32) ;; %f0
+ (FCC_REG 96) ;; %fcc0
+ (ICC_REG 100) ;; %icc
+
+ ;; These are used with unspec.
+ (UNSPEC_PIC 0) ;; movsi_{lo_sum,high}_pic
+ ;; pic_lo_sum_di, pic_sethi_di
+ ;; 1 ;; update_return
+ (UNSPEC_GET_PC 2)
+ (UNSPEC_PIC_LABEL_REF 5) ;; movsi_{,lo_sum_,high_}pic_label_ref
+ (UNSPEC_SETH44 6)
+ (UNSPEC_SETM44 7)
+ (UNSPEC_SETHH 9)
+ (UNSPEC_SETLM 10)
+ (UNSPEC_EMBMEDANY_SETHI 11) ;; embmedany_sethi, embmedany_brsum
+ (UNSPEC_EMBMEDANY_TEXTUHI 13)
+ (UNSPEC_EMBMEDANY_TEXTHI 14)
+ (UNSPEC_EMBMEDANY_TEXTULO 15)
+ ;; 16 ;; embmedany_textlo
+ (UNSPEC_SETHM 18)
+ ;; 19 ;; setlo
+
+ ;; These are used with unspec_volatile.
+ (UNSPECV_BLOCKAGE 0)
+ (UNSPECV_FLUSH_REG_WIND 1)
+ (UNSPECV_GOTO_HANDLER 2)
+ ;; (UNSPECV_GOTO_HANDLER_V9 3) ;; not used?
+ (UNSPECV_FLUSH 3)
+ (UNSPECV_DO_BUILTIN_SETJMP 5)
+])
+
;; The upper 32 fp regs on the v9 can't hold SFmode values. To deal with this
;; a second register class, EXTRA_FP_REGS, exists for the v9 chip. The name
@@ -571,7 +583,7 @@
;; Put cmpsi first among compare insns so it matches two CONST_INT operands.
(define_expand "cmpsi"
- [(set (reg:CC 100)
+ [(set (reg:CC ICC_REG)
(compare:CC (match_operand:SI 0 "register_operand" "")
(match_operand:SI 1 "arith_operand" "")))]
""
@@ -583,7 +595,7 @@
}")
(define_expand "cmpdi"
- [(set (reg:CCX 100)
+ [(set (reg:CCX ICC_REG)
(compare:CCX (match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "arith_double_operand" "")))]
"TARGET_ARCH64"
@@ -596,7 +608,7 @@
(define_expand "cmpsf"
;; The 96 here isn't ever used by anyone.
- [(set (reg:CCFP 96)
+ [(set (reg:CCFP FCC_REG)
(compare:CCFP (match_operand:SF 0 "register_operand" "")
(match_operand:SF 1 "register_operand" "")))]
"TARGET_FPU"
@@ -609,7 +621,7 @@
(define_expand "cmpdf"
;; The 96 here isn't ever used by anyone.
- [(set (reg:CCFP 96)
+ [(set (reg:CCFP FCC_REG)
(compare:CCFP (match_operand:DF 0 "register_operand" "")
(match_operand:DF 1 "register_operand" "")))]
"TARGET_FPU"
@@ -622,7 +634,7 @@
(define_expand "cmptf"
;; The 96 here isn't ever used by anyone.
- [(set (reg:CCFP 96)
+ [(set (reg:CCFP FCC_REG)
(compare:CCFP (match_operand:TF 0 "register_operand" "")
(match_operand:TF 1 "register_operand" "")))]
"TARGET_FPU"
@@ -636,7 +648,7 @@
;; Now the compare DEFINE_INSNs.
(define_insn "*cmpsi_insn"
- [(set (reg:CC 100)
+ [(set (reg:CC ICC_REG)
(compare:CC (match_operand:SI 0 "register_operand" "r")
(match_operand:SI 1 "arith_operand" "rI")))]
""
@@ -644,7 +656,7 @@
[(set_attr "type" "compare")])
(define_insn "*cmpdi_sp64"
- [(set (reg:CCX 100)
+ [(set (reg:CCX ICC_REG)
(compare:CCX (match_operand:DI 0 "register_operand" "r")
(match_operand:DI 1 "arith_double_operand" "rHI")))]
"TARGET_ARCH64"
@@ -745,7 +757,7 @@
(match_operand:SI 2 "register_operand" "")))
(parallel [(set (match_operand:SI 0 "register_operand" "")
(eq:SI (match_dup 3) (const_int 0)))
- (clobber (reg:CC 100))])]
+ (clobber (reg:CC ICC_REG))])]
""
"{ operands[3] = gen_reg_rtx (SImode); }")
@@ -764,7 +776,7 @@
(match_operand:SI 2 "register_operand" "")))
(parallel [(set (match_operand:SI 0 "register_operand" "")
(ne:SI (match_dup 3) (const_int 0)))
- (clobber (reg:CC 100))])]
+ (clobber (reg:CC ICC_REG))])]
""
"{ operands[3] = gen_reg_rtx (SImode); }")
@@ -801,7 +813,7 @@
(match_operand:SI 2 "register_operand" "")))
(parallel [(set (match_operand:DI 0 "register_operand" "")
(eq:DI (match_dup 3) (const_int 0)))
- (clobber (reg:CC 100))])]
+ (clobber (reg:CC ICC_REG))])]
"TARGET_ARCH64"
"{ operands[3] = gen_reg_rtx (SImode); }")
@@ -811,7 +823,7 @@
(match_operand:SI 2 "register_operand" "")))
(parallel [(set (match_operand:DI 0 "register_operand" "")
(ne:DI (match_dup 3) (const_int 0)))
- (clobber (reg:CC 100))])]
+ (clobber (reg:CC ICC_REG))])]
"TARGET_ARCH64"
"{ operands[3] = gen_reg_rtx (SImode); }")
@@ -1114,7 +1126,7 @@
[(set (match_operand:SI 0 "register_operand" "=r")
(ne:SI (match_operand:SI 1 "register_operand" "r")
(const_int 0)))
- (clobber (reg:CC 100))]
+ (clobber (reg:CC ICC_REG))]
""
"#"
[(set_attr "length" "2")])
@@ -1123,18 +1135,18 @@
[(set (match_operand:SI 0 "register_operand" "")
(ne:SI (match_operand:SI 1 "register_operand" "")
(const_int 0)))
- (clobber (reg:CC 100))]
+ (clobber (reg:CC ICC_REG))]
""
- [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
+ [(set (reg:CC_NOOV ICC_REG) (compare:CC_NOOV (neg:SI (match_dup 1))
(const_int 0)))
- (set (match_dup 0) (ltu:SI (reg:CC 100) (const_int 0)))]
+ (set (match_dup 0) (ltu:SI (reg:CC ICC_REG) (const_int 0)))]
"")
(define_insn "*neg_snesi_zero"
[(set (match_operand:SI 0 "register_operand" "=r")
(neg:SI (ne:SI (match_operand:SI 1 "register_operand" "r")
(const_int 0))))
- (clobber (reg:CC 100))]
+ (clobber (reg:CC ICC_REG))]
""
"#"
[(set_attr "length" "2")])
@@ -1143,18 +1155,18 @@
[(set (match_operand:SI 0 "register_operand" "")
(neg:SI (ne:SI (match_operand:SI 1 "register_operand" "")
(const_int 0))))
- (clobber (reg:CC 100))]
+ (clobber (reg:CC ICC_REG))]
""
- [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
+ [(set (reg:CC_NOOV ICC_REG) (compare:CC_NOOV (neg:SI (match_dup 1))
(const_int 0)))
- (set (match_dup 0) (neg:SI (ltu:SI (reg:CC 100) (const_int 0))))]
+ (set (match_dup 0) (neg:SI (ltu:SI (reg:CC ICC_REG) (const_int 0))))]
"")
(define_insn "*snesi_zero_extend"
[(set (match_operand:DI 0 "register_operand" "=r")
(ne:DI (match_operand:SI 1 "register_operand" "r")
(const_int 0)))
- (clobber (reg:CC 100))]
+ (clobber (reg:CC ICC_REG))]
"TARGET_ARCH64"
"#"
[(set_attr "type" "unary")
@@ -1164,13 +1176,13 @@
[(set (match_operand:DI 0 "register_operand" "")
(ne:DI (match_operand:SI 1 "register_operand" "")
(const_int 0)))
- (clobber (reg:CC 100))]
+ (clobber (reg:CC ICC_REG))]
"TARGET_ARCH64"
- [(set (reg:CC_NOOV 100) (compare:CC_NOOV (minus:SI (const_int 0) (match_dup 1))
+ [(set (reg:CC_NOOV ICC_REG) (compare:CC_NOOV (minus:SI (const_int 0) (match_dup 1))
(const_int 0)))
(set (match_dup 0) (zero_extend:DI (plus:SI (plus:SI (const_int 0)
(const_int 0))
- (ltu:SI (reg:CC_NOOV 100)
+ (ltu:SI (reg:CC_NOOV ICC_REG)
(const_int 0)))))]
"")
@@ -1244,7 +1256,7 @@
[(set (match_operand:SI 0 "register_operand" "=r")
(eq:SI (match_operand:SI 1 "register_operand" "r")
(const_int 0)))
- (clobber (reg:CC 100))]
+ (clobber (reg:CC ICC_REG))]
""
"#"
[(set_attr "length" "2")])
@@ -1253,18 +1265,18 @@
[(set (match_operand:SI 0 "register_operand" "")
(eq:SI (match_operand:SI 1 "register_operand" "")
(const_int 0)))
- (clobber (reg:CC 100))]
+ (clobber (reg:CC ICC_REG))]
""
- [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
+ [(set (reg:CC_NOOV ICC_REG) (compare:CC_NOOV (neg:SI (match_dup 1))
(const_int 0)))
- (set (match_dup 0) (geu:SI (reg:CC 100) (const_int 0)))]
+ (set (match_dup 0) (geu:SI (reg:CC ICC_REG) (const_int 0)))]
"")
(define_insn "*neg_seqsi_zero"
[(set (match_operand:SI 0 "register_operand" "=r")
(neg:SI (eq:SI (match_operand:SI 1 "register_operand" "r")
(const_int 0))))
- (clobber (reg:CC 100))]
+ (clobber (reg:CC ICC_REG))]
""
"#"
[(set_attr "length" "2")])
@@ -1273,18 +1285,18 @@
[(set (match_operand:SI 0 "register_operand" "")
(neg:SI (eq:SI (match_operand:SI 1 "register_operand" "")
(const_int 0))))
- (clobber (reg:CC 100))]
+ (clobber (reg:CC ICC_REG))]
""
- [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
+ [(set (reg:CC_NOOV ICC_REG) (compare:CC_NOOV (neg:SI (match_dup 1))
(const_int 0)))
- (set (match_dup 0) (neg:SI (geu:SI (reg:CC 100) (const_int 0))))]
+ (set (match_dup 0) (neg:SI (geu:SI (reg:CC ICC_REG) (const_int 0))))]
"")
(define_insn "*seqsi_zero_extend"
[(set (match_operand:DI 0 "register_operand" "=r")
(eq:DI (match_operand:SI 1 "register_operand" "r")
(const_int 0)))
- (clobber (reg:CC 100))]
+ (clobber (reg:CC ICC_REG))]
"TARGET_ARCH64"
"#"
[(set_attr "type" "unary")
@@ -1294,13 +1306,13 @@
[(set (match_operand:DI 0 "register_operand" "")
(eq:DI (match_operand:SI 1 "register_operand" "")
(const_int 0)))
- (clobber (reg:CC 100))]
+ (clobber (reg:CC ICC_REG))]
"TARGET_ARCH64"
- [(set (reg:CC_NOOV 100) (compare:CC_NOOV (minus:SI (const_int 0) (match_dup 1))
+ [(set (reg:CC_NOOV ICC_REG) (compare:CC_NOOV (minus:SI (const_int 0) (match_dup 1))
(const_int 0)))
(set (match_dup 0) (zero_extend:DI (minus:SI (minus:SI (const_int 0)
(const_int -1))
- (ltu:SI (reg:CC_NOOV 100)
+ (ltu:SI (reg:CC_NOOV ICC_REG)
(const_int 0)))))]
"")
@@ -1379,7 +1391,7 @@
(plus:SI (ne:SI (match_operand:SI 1 "register_operand" "r")
(const_int 0))
(match_operand:SI 2 "register_operand" "r")))
- (clobber (reg:CC 100))]
+ (clobber (reg:CC ICC_REG))]
""
"#"
[(set_attr "length" "2")])
@@ -1389,11 +1401,11 @@
(plus:SI (ne:SI (match_operand:SI 1 "register_operand" "")
(const_int 0))
(match_operand:SI 2 "register_operand" "")))
- (clobber (reg:CC 100))]
+ (clobber (reg:CC ICC_REG))]
""
- [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
+ [(set (reg:CC_NOOV ICC_REG) (compare:CC_NOOV (neg:SI (match_dup 1))
(const_int 0)))
- (set (match_dup 0) (plus:SI (ltu:SI (reg:CC 100) (const_int 0))
+ (set (match_dup 0) (plus:SI (ltu:SI (reg:CC ICC_REG) (const_int 0))
(match_dup 2)))]
"")
@@ -1402,7 +1414,7 @@
(minus:SI (match_operand:SI 2 "register_operand" "r")
(ne:SI (match_operand:SI 1 "register_operand" "r")
(const_int 0))))
- (clobber (reg:CC 100))]
+ (clobber (reg:CC ICC_REG))]
""
"#"
[(set_attr "length" "2")])
@@ -1412,12 +1424,12 @@
(minus:SI (match_operand:SI 2 "register_operand" "")
(ne:SI (match_operand:SI 1 "register_operand" "")
(const_int 0))))
- (clobber (reg:CC 100))]
+ (clobber (reg:CC ICC_REG))]
""
- [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
+ [(set (reg:CC_NOOV ICC_REG) (compare:CC_NOOV (neg:SI (match_dup 1))
(const_int 0)))
(set (match_dup 0) (minus:SI (match_dup 2)
- (ltu:SI (reg:CC 100) (const_int 0))))]
+ (ltu:SI (reg:CC ICC_REG) (const_int 0))))]
"")
(define_insn "*x_plus_i_eq_0"
@@ -1425,7 +1437,7 @@
(plus:SI (eq:SI (match_operand:SI 1 "register_operand" "r")
(const_int 0))
(match_operand:SI 2 "register_operand" "r")))
- (clobber (reg:CC 100))]
+ (clobber (reg:CC ICC_REG))]
""
"#"
[(set_attr "length" "2")])
@@ -1435,11 +1447,11 @@
(plus:SI (eq:SI (match_operand:SI 1 "register_operand" "")
(const_int 0))
(match_operand:SI 2 "register_operand" "")))
- (clobber (reg:CC 100))]
+ (clobber (reg:CC ICC_REG))]
""
- [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
+ [(set (reg:CC_NOOV ICC_REG) (compare:CC_NOOV (neg:SI (match_dup 1))
(const_int 0)))
- (set (match_dup 0) (plus:SI (geu:SI (reg:CC 100) (const_int 0))
+ (set (match_dup 0) (plus:SI (geu:SI (reg:CC ICC_REG) (const_int 0))
(match_dup 2)))]
"")
@@ -1448,7 +1460,7 @@
(minus:SI (match_operand:SI 2 "register_operand" "r")
(eq:SI (match_operand:SI 1 "register_operand" "r")
(const_int 0))))
- (clobber (reg:CC 100))]
+ (clobber (reg:CC ICC_REG))]
""
"#"
[(set_attr "length" "2")])
@@ -1458,12 +1470,12 @@
(minus:SI (match_operand:SI 2 "register_operand" "")
(eq:SI (match_operand:SI 1 "register_operand" "")
(const_int 0))))
- (clobber (reg:CC 100))]
+ (clobber (reg:CC ICC_REG))]
""
- [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
+ [(set (reg:CC_NOOV ICC_REG) (compare:CC_NOOV (neg:SI (match_dup 1))
(const_int 0)))
(set (match_dup 0) (minus:SI (match_dup 2)
- (geu:SI (reg:CC 100) (const_int 0))))]
+ (geu:SI (reg:CC ICC_REG) (const_int 0))))]
"")
;; We can also do GEU and LTU directly, but these operate after a compare.
@@ -1472,7 +1484,7 @@
(define_insn "*sltu_insn"
[(set (match_operand:SI 0 "register_operand" "=r")
- (ltu:SI (reg:CC 100) (const_int 0)))]
+ (ltu:SI (reg:CC ICC_REG) (const_int 0)))]
""
"addx\\t%%g0, 0, %0"
[(set_attr "type" "misc")
@@ -1480,7 +1492,7 @@
(define_insn "*neg_sltu_insn"
[(set (match_operand:SI 0 "register_operand" "=r")
- (neg:SI (ltu:SI (reg:CC 100) (const_int 0))))]
+ (neg:SI (ltu:SI (reg:CC ICC_REG) (const_int 0))))]
""
"subx\\t%%g0, 0, %0"
[(set_attr "type" "misc")
@@ -1489,7 +1501,7 @@
;; ??? Combine should canonicalize these next two to the same pattern.
(define_insn "*neg_sltu_minus_x"
[(set (match_operand:SI 0 "register_operand" "=r")
- (minus:SI (neg:SI (ltu:SI (reg:CC 100) (const_int 0)))
+ (minus:SI (neg:SI (ltu:SI (reg:CC ICC_REG) (const_int 0)))
(match_operand:SI 1 "arith_operand" "rI")))]
""
"subx\\t%%g0, %1, %0"
@@ -1498,7 +1510,7 @@
(define_insn "*neg_sltu_plus_x"
[(set (match_operand:SI 0 "register_operand" "=r")
- (neg:SI (plus:SI (ltu:SI (reg:CC 100) (const_int 0))
+ (neg:SI (plus:SI (ltu:SI (reg:CC ICC_REG) (const_int 0))
(match_operand:SI 1 "arith_operand" "rI"))))]
""
"subx\\t%%g0, %1, %0"
@@ -1507,7 +1519,7 @@
(define_insn "*sgeu_insn"
[(set (match_operand:SI 0 "register_operand" "=r")
- (geu:SI (reg:CC 100) (const_int 0)))]
+ (geu:SI (reg:CC ICC_REG) (const_int 0)))]
""
"subx\\t%%g0, -1, %0"
[(set_attr "type" "misc")
@@ -1515,7 +1527,7 @@
(define_insn "*neg_sgeu_insn"
[(set (match_operand:SI 0 "register_operand" "=r")
- (neg:SI (geu:SI (reg:CC 100) (const_int 0))))]
+ (neg:SI (geu:SI (reg:CC ICC_REG) (const_int 0))))]
""
"addx\\t%%g0, -1, %0"
[(set_attr "type" "misc")
@@ -1527,7 +1539,7 @@
(define_insn "*sltu_plus_x"
[(set (match_operand:SI 0 "register_operand" "=r")
- (plus:SI (ltu:SI (reg:CC 100) (const_int 0))
+ (plus:SI (ltu:SI (reg:CC ICC_REG) (const_int 0))
(match_operand:SI 1 "arith_operand" "rI")))]
""
"addx\\t%%g0, %1, %0"
@@ -1536,7 +1548,7 @@
(define_insn "*sltu_plus_x_plus_y"
[(set (match_operand:SI 0 "register_operand" "=r")
- (plus:SI (ltu:SI (reg:CC 100) (const_int 0))
+ (plus:SI (ltu:SI (reg:CC ICC_REG) (const_int 0))
(plus:SI (match_operand:SI 1 "arith_operand" "%r")
(match_operand:SI 2 "arith_operand" "rI"))))]
""
@@ -1547,7 +1559,7 @@
(define_insn "*x_minus_sltu"
[(set (match_operand:SI 0 "register_operand" "=r")
(minus:SI (match_operand:SI 1 "register_operand" "r")
- (ltu:SI (reg:CC 100) (const_int 0))))]
+ (ltu:SI (reg:CC ICC_REG) (const_int 0))))]
""
"subx\\t%1, 0, %0"
[(set_attr "type" "misc")
@@ -1558,7 +1570,7 @@
[(set (match_operand:SI 0 "register_operand" "=r")
(minus:SI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
(match_operand:SI 2 "arith_operand" "rI"))
- (ltu:SI (reg:CC 100) (const_int 0))))]
+ (ltu:SI (reg:CC ICC_REG) (const_int 0))))]
""
"subx\\t%r1, %2, %0"
[(set_attr "type" "misc")
@@ -1567,7 +1579,7 @@
(define_insn "*x_minus_sltu_plus_y"
[(set (match_operand:SI 0 "register_operand" "=r")
(minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
- (plus:SI (ltu:SI (reg:CC 100) (const_int 0))
+ (plus:SI (ltu:SI (reg:CC ICC_REG) (const_int 0))
(match_operand:SI 2 "arith_operand" "rI"))))]
""
"subx\\t%r1, %2, %0"
@@ -1576,7 +1588,7 @@
(define_insn "*sgeu_plus_x"
[(set (match_operand:SI 0 "register_operand" "=r")
- (plus:SI (geu:SI (reg:CC 100) (const_int 0))
+ (plus:SI (geu:SI (reg:CC ICC_REG) (const_int 0))
(match_operand:SI 1 "register_operand" "r")))]
""
"subx\\t%1, -1, %0"
@@ -1586,7 +1598,7 @@
(define_insn "*x_minus_sgeu"
[(set (match_operand:SI 0 "register_operand" "=r")
(minus:SI (match_operand:SI 1 "register_operand" "r")
- (geu:SI (reg:CC 100) (const_int 0))))]
+ (geu:SI (reg:CC ICC_REG) (const_int 0))))]
""
"addx\\t%1, -1, %0"
[(set_attr "type" "misc")
@@ -2082,9 +2094,9 @@
;; Load program counter insns.
(define_insn "get_pc"
- [(clobber (reg:SI 15))
+ [(clobber (reg:SI O7_REG))
(set (match_operand 0 "register_operand" "=r")
- (unspec [(match_operand 1 "" "") (match_operand 2 "" "")] 2))]
+ (unspec [(match_operand 1 "" "") (match_operand 2 "" "")] UNSPEC_GET_PC))]
"flag_pic && REGNO (operands[0]) == 23"
"sethi\\t%%hi(%a1-4), %0\\n\\tcall\\t%a2\\n\\tadd\\t%0, %%lo(%a1+4), %0"
[(set_attr "length" "3")])
@@ -2377,7 +2389,7 @@
(define_insn "movsi_lo_sum_pic"
[(set (match_operand:SI 0 "register_operand" "=r")
(lo_sum:SI (match_operand:SI 1 "register_operand" "r")
- (unspec:SI [(match_operand:SI 2 "immediate_operand" "in")] 0)))]
+ (unspec:SI [(match_operand:SI 2 "immediate_operand" "in")] UNSPEC_PIC)))]
"flag_pic"
"or\\t%1, %%lo(%a2), %0"
[(set_attr "type" "ialu")
@@ -2385,7 +2397,7 @@
(define_insn "movsi_high_pic"
[(set (match_operand:SI 0 "register_operand" "=r")
- (high:SI (unspec:SI [(match_operand 1 "" "")] 0)))]
+ (high:SI (unspec:SI [(match_operand 1 "" "")] UNSPEC_PIC)))]
"flag_pic && check_pic (1)"
"sethi\\t%%hi(%a1), %0"
[(set_attr "type" "move")
@@ -2394,9 +2406,9 @@
(define_expand "movsi_pic_label_ref"
[(set (match_dup 3) (high:SI
(unspec:SI [(match_operand:SI 1 "label_ref_operand" "")
- (match_dup 2)] 5)))
+ (match_dup 2)] UNSPEC_PIC_LABEL_REF)))
(set (match_dup 4) (lo_sum:SI (match_dup 3)
- (unspec:SI [(match_dup 1) (match_dup 2)] 5)))
+ (unspec:SI [(match_dup 1) (match_dup 2)] UNSPEC_PIC_LABEL_REF)))
(set (match_operand:SI 0 "register_operand" "=r")
(minus:SI (match_dup 5) (match_dup 4)))]
"flag_pic"
@@ -2421,7 +2433,7 @@
[(set (match_operand:SI 0 "register_operand" "=r")
(high:SI
(unspec:SI [(match_operand:SI 1 "label_ref_operand" "")
- (match_operand:SI 2 "" "")] 5)))]
+ (match_operand:SI 2 "" "")] UNSPEC_PIC_LABEL_REF)))]
"flag_pic"
"sethi\\t%%hi(%a2-(%a1-.)), %0"
[(set_attr "type" "move")
@@ -2431,7 +2443,7 @@
[(set (match_operand:SI 0 "register_operand" "=r")
(lo_sum:SI (match_operand:SI 1 "register_operand" "r")
(unspec:SI [(match_operand:SI 2 "label_ref_operand" "")
- (match_operand:SI 3 "" "")] 5)))]
+ (match_operand:SI 3 "" "")] UNSPEC_PIC_LABEL_REF)))]
"flag_pic"
"or\\t%1, %%lo(%a3-(%a2-.)), %0"
[(set_attr "type" "ialu")
@@ -2614,9 +2626,9 @@
(define_expand "movdi_pic_label_ref"
[(set (match_dup 3) (high:DI
(unspec:DI [(match_operand:DI 1 "label_ref_operand" "")
- (match_dup 2)] 5)))
+ (match_dup 2)] UNSPEC_PIC_LABEL_REF)))
(set (match_dup 4) (lo_sum:DI (match_dup 3)
- (unspec:DI [(match_dup 1) (match_dup 2)] 5)))
+ (unspec:DI [(match_dup 1) (match_dup 2)] UNSPEC_PIC_LABEL_REF)))
(set (match_operand:DI 0 "register_operand" "=r")
(minus:DI (match_dup 5) (match_dup 4)))]
"TARGET_ARCH64 && flag_pic"
@@ -2641,7 +2653,7 @@
[(set (match_operand:DI 0 "register_operand" "=r")
(high:DI
(unspec:DI [(match_operand:DI 1 "label_ref_operand" "")
- (match_operand:DI 2 "" "")] 5)))]
+ (match_operand:DI 2 "" "")] UNSPEC_PIC_LABEL_REF)))]
"TARGET_ARCH64 && flag_pic"
"sethi\\t%%hi(%a2-(%a1-.)), %0"
[(set_attr "type" "move")
@@ -2651,7 +2663,7 @@
[(set (match_operand:DI 0 "register_operand" "=r")
(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
(unspec:DI [(match_operand:DI 2 "label_ref_operand" "")
- (match_operand:DI 3 "" "")] 5)))]
+ (match_operand:DI 3 "" "")] UNSPEC_PIC_LABEL_REF)))]
"TARGET_ARCH64 && flag_pic"
"or\\t%1, %%lo(%a3-(%a2-.)), %0"
[(set_attr "type" "ialu")
@@ -2663,7 +2675,7 @@
(define_insn "movdi_lo_sum_pic"
[(set (match_operand:DI 0 "register_operand" "=r")
(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
- (unspec:DI [(match_operand:DI 2 "immediate_operand" "in")] 0)))]
+ (unspec:DI [(match_operand:DI 2 "immediate_operand" "in")] UNSPEC_PIC)))]
"TARGET_ARCH64 && flag_pic"
"or\\t%1, %%lo(%a2), %0"
[(set_attr "type" "ialu")
@@ -2671,7 +2683,7 @@
(define_insn "movdi_high_pic"
[(set (match_operand:DI 0 "register_operand" "=r")
- (high:DI (unspec:DI [(match_operand 1 "" "")] 0)))]
+ (high:DI (unspec:DI [(match_operand 1 "" "")] UNSPEC_PIC)))]
"TARGET_ARCH64 && flag_pic && check_pic (1)"
"sethi\\t%%hi(%a1), %0"
[(set_attr "type" "move")
@@ -2704,7 +2716,7 @@
(define_insn "seth44"
[(set (match_operand:DI 0 "register_operand" "=r")
- (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] 6)))]
+ (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] UNSPEC_SETH44)))]
"TARGET_CM_MEDMID"
"sethi\\t%%h44(%a1), %0"
[(set_attr "type" "move")
@@ -2713,7 +2725,7 @@
(define_insn "setm44"
[(set (match_operand:DI 0 "register_operand" "=r")
(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
- (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] 7)))]
+ (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] UNSPEC_SETM44)))]
"TARGET_CM_MEDMID"
"or\\t%1, %%m44(%a2), %0"
[(set_attr "type" "move")
@@ -2730,7 +2742,7 @@
(define_insn "sethh"
[(set (match_operand:DI 0 "register_operand" "=r")
- (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] 9)))]
+ (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] UNSPEC_SETHH)))]
"TARGET_CM_MEDANY"
"sethi\\t%%hh(%a1), %0"
[(set_attr "type" "move")
@@ -2738,7 +2750,7 @@
(define_insn "setlm"
[(set (match_operand:DI 0 "register_operand" "=r")
- (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] 10)))]
+ (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] UNSPEC_SETLM)))]
"TARGET_CM_MEDANY"
"sethi\\t%%lm(%a1), %0"
[(set_attr "type" "move")
@@ -2747,7 +2759,7 @@
(define_insn "sethm"
[(set (match_operand:DI 0 "register_operand" "=r")
(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
- (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] 18)))]
+ (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] UNSPEC_SETHM)))]
"TARGET_CM_MEDANY"
"or\\t%1, %%hm(%a2), %0"
[(set_attr "type" "ialu")
@@ -2764,7 +2776,7 @@
(define_insn "embmedany_sethi"
[(set (match_operand:DI 0 "register_operand" "=r")
- (high:DI (unspec:DI [(match_operand:DI 1 "data_segment_operand" "")] 11)))]
+ (high:DI (unspec:DI [(match_operand:DI 1 "data_segment_operand" "")] UNSPEC_EMBMEDANY_SETHI)))]
"TARGET_CM_EMBMEDANY && check_pic (1)"
"sethi\\t%%hi(%a1), %0"
[(set_attr "type" "move")
@@ -2781,14 +2793,14 @@
(define_insn "embmedany_brsum"
[(set (match_operand:DI 0 "register_operand" "=r")
- (unspec:DI [(match_operand:DI 1 "register_operand" "r")] 11))]
+ (unspec:DI [(match_operand:DI 1 "register_operand" "r")] UNSPEC_EMBMEDANY_SETHI))]
"TARGET_CM_EMBMEDANY"
"add\\t%1, %_, %0"
[(set_attr "length" "1")])
(define_insn "embmedany_textuhi"
[(set (match_operand:DI 0 "register_operand" "=r")
- (high:DI (unspec:DI [(match_operand:DI 1 "text_segment_operand" "")] 13)))]
+ (high:DI (unspec:DI [(match_operand:DI 1 "text_segment_operand" "")] UNSPEC_EMBMEDANY_TEXTUHI)))]
"TARGET_CM_EMBMEDANY && check_pic (1)"
"sethi\\t%%uhi(%a1), %0"
[(set_attr "type" "move")
@@ -2796,7 +2808,7 @@
(define_insn "embmedany_texthi"
[(set (match_operand:DI 0 "register_operand" "=r")
- (high:DI (unspec:DI [(match_operand:DI 1 "text_segment_operand" "")] 14)))]
+ (high:DI (unspec:DI [(match_operand:DI 1 "text_segment_operand" "")] UNSPEC_EMBMEDANY_TEXTHI)))]
"TARGET_CM_EMBMEDANY && check_pic (1)"
"sethi\\t%%hi(%a1), %0"
[(set_attr "type" "move")
@@ -2805,7 +2817,7 @@
(define_insn "embmedany_textulo"
[(set (match_operand:DI 0 "register_operand" "=r")
(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
- (unspec:DI [(match_operand:DI 2 "text_segment_operand" "")] 15)))]
+ (unspec:DI [(match_operand:DI 2 "text_segment_operand" "")] UNSPEC_EMBMEDANY_TEXTULO)))]
"TARGET_CM_EMBMEDANY"
"or\\t%1, %%ulo(%a2), %0"
[(set_attr "type" "ialu")
@@ -4709,7 +4721,7 @@
;; Simplify comparisons of extended values.
(define_insn "*cmp_zero_extendqisi2"
- [(set (reg:CC 100)
+ [(set (reg:CC ICC_REG)
(compare:CC (zero_extend:SI (match_operand:QI 0 "register_operand" "r"))
(const_int 0)))]
""
@@ -4718,7 +4730,7 @@
(set_attr "length" "1")])
(define_insn "*cmp_zero_qi"
- [(set (reg:CC 100)
+ [(set (reg:CC ICC_REG)
(compare:CC (match_operand:QI 0 "register_operand" "r")
(const_int 0)))]
""
@@ -4727,7 +4739,7 @@
(set_attr "length" "1")])
(define_insn "*cmp_zero_extendqisi2_set"
- [(set (reg:CC 100)
+ [(set (reg:CC ICC_REG)
(compare:CC (zero_extend:SI (match_operand:QI 1 "register_operand" "r"))
(const_int 0)))
(set (match_operand:SI 0 "register_operand" "=r")
@@ -4738,7 +4750,7 @@
(set_attr "length" "1")])
(define_insn "*cmp_zero_extendqisi2_andcc_set"
- [(set (reg:CC 100)
+ [(set (reg:CC ICC_REG)
(compare:CC (and:SI (match_operand:SI 1 "register_operand" "r")
(const_int 255))
(const_int 0)))
@@ -4750,7 +4762,7 @@
(set_attr "length" "1")])
(define_insn "*cmp_zero_extendqidi2"
- [(set (reg:CCX 100)
+ [(set (reg:CCX ICC_REG)
(compare:CCX (zero_extend:DI (match_operand:QI 0 "register_operand" "r"))
(const_int 0)))]
"TARGET_ARCH64"
@@ -4759,7 +4771,7 @@
(set_attr "length" "1")])
(define_insn "*cmp_zero_qi_sp64"
- [(set (reg:CCX 100)
+ [(set (reg:CCX ICC_REG)
(compare:CCX (match_operand:QI 0 "register_operand" "r")
(const_int 0)))]
"TARGET_ARCH64"
@@ -4768,7 +4780,7 @@
(set_attr "length" "1")])
(define_insn "*cmp_zero_extendqidi2_set"
- [(set (reg:CCX 100)
+ [(set (reg:CCX ICC_REG)
(compare:CCX (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=r")
@@ -4779,7 +4791,7 @@
(set_attr "length" "1")])
(define_insn "*cmp_zero_extendqidi2_andcc_set"
- [(set (reg:CCX 100)
+ [(set (reg:CCX ICC_REG)
(compare:CCX (and:DI (match_operand:DI 1 "register_operand" "r")
(const_int 255))
(const_int 0)))
@@ -4793,7 +4805,7 @@
;; Similarly, handle {SI,DI}->QI mode truncation followed by a compare.
(define_insn "*cmp_siqi_trunc"
- [(set (reg:CC 100)
+ [(set (reg:CC ICC_REG)
(compare:CC (subreg:QI (match_operand:SI 0 "register_operand" "r") 0)
(const_int 0)))]
""
@@ -4802,7 +4814,7 @@
(set_attr "length" "1")])
(define_insn "*cmp_siqi_trunc_set"
- [(set (reg:CC 100)
+ [(set (reg:CC ICC_REG)
(compare:CC (subreg:QI (match_operand:SI 1 "register_operand" "r") 0)
(const_int 0)))
(set (match_operand:QI 0 "register_operand" "=r")
@@ -4813,7 +4825,7 @@
(set_attr "length" "1")])
(define_insn "*cmp_diqi_trunc"
- [(set (reg:CC 100)
+ [(set (reg:CC ICC_REG)
(compare:CC (subreg:QI (match_operand:DI 0 "register_operand" "r") 0)
(const_int 0)))]
"TARGET_ARCH64"
@@ -4822,7 +4834,7 @@
(set_attr "length" "1")])
(define_insn "*cmp_diqi_trunc_set"
- [(set (reg:CC 100)
+ [(set (reg:CC ICC_REG)
(compare:CC (subreg:QI (match_operand:DI 1 "register_operand" "r") 0)
(const_int 0)))
(set (match_operand:QI 0 "register_operand" "=r")
@@ -5015,7 +5027,7 @@
;; because combine uses this as a canonical form.
(define_insn "*cmp_zero_extract"
- [(set (reg:CC 100)
+ [(set (reg:CC ICC_REG)
(compare:CC
(zero_extract:SI (match_operand:SI 0 "register_operand" "r")
(match_operand:SI 1 "small_int_or_double" "n")
@@ -5043,7 +5055,7 @@
(set_attr "length" "1")])
(define_insn "*cmp_zero_extract_sp64"
- [(set (reg:CCX 100)
+ [(set (reg:CCX ICC_REG)
(compare:CCX
(zero_extract:DI (match_operand:DI 0 "register_operand" "r")
(match_operand:SI 1 "small_int_or_double" "n")
@@ -5573,7 +5585,7 @@
[(set (match_operand:DI 0 "register_operand" "=r")
(plus:DI (match_operand:DI 1 "arith_double_operand" "%r")
(match_operand:DI 2 "arith_double_operand" "rHI")))
- (clobber (reg:CC 100))]
+ (clobber (reg:CC ICC_REG))]
"! TARGET_ARCH64"
"#"
[(set_attr "length" "2")])
@@ -5582,9 +5594,9 @@
[(set (match_operand:DI 0 "register_operand" "=r")
(plus:DI (match_operand:DI 1 "arith_double_operand" "%r")
(match_operand:DI 2 "arith_double_operand" "rHI")))
- (clobber (reg:CC 100))]
+ (clobber (reg:CC ICC_REG))]
"! TARGET_ARCH64 && reload_completed"
- [(parallel [(set (reg:CC_NOOV 100)
+ [(parallel [(set (reg:CC_NOOV ICC_REG)
(compare:CC_NOOV (plus:SI (match_dup 4)
(match_dup 5))
(const_int 0)))
@@ -5593,7 +5605,7 @@
(set (match_dup 6)
(plus:SI (plus:SI (match_dup 7)
(match_dup 8))
- (ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
+ (ltu:SI (reg:CC_NOOV ICC_REG) (const_int 0))))]
"
{
operands[3] = gen_lowpart (SImode, operands[0]);
@@ -5618,9 +5630,9 @@
[(set (match_operand:DI 0 "register_operand" "=r")
(minus:DI (match_operand:DI 1 "arith_double_operand" "r")
(match_operand:DI 2 "arith_double_operand" "rHI")))
- (clobber (reg:CC 100))]
+ (clobber (reg:CC ICC_REG))]
"! TARGET_ARCH64 && reload_completed"
- [(parallel [(set (reg:CC_NOOV 100)
+ [(parallel [(set (reg:CC_NOOV ICC_REG)
(compare:CC_NOOV (minus:SI (match_dup 4)
(match_dup 5))
(const_int 0)))
@@ -5629,7 +5641,7 @@
(set (match_dup 6)
(minus:SI (minus:SI (match_dup 7)
(match_dup 8))
- (ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
+ (ltu:SI (reg:CC_NOOV ICC_REG) (const_int 0))))]
"
{
operands[3] = gen_lowpart (SImode, operands[0]);
@@ -5655,7 +5667,7 @@
[(set (match_operand:SI 0 "register_operand" "=r")
(plus:SI (plus:SI (match_operand:SI 1 "arith_operand" "%r")
(match_operand:SI 2 "arith_operand" "rI"))
- (ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
+ (ltu:SI (reg:CC_NOOV ICC_REG) (const_int 0))))]
""
"addx\\t%1, %2, %0"
[(set_attr "type" "unary")
@@ -5665,7 +5677,7 @@
[(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI (plus:SI (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
(match_operand:SI 2 "arith_operand" "rI"))
- (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))]
+ (ltu:SI (reg:CC_NOOV ICC_REG) (const_int 0)))))]
"! TARGET_ARCH64"
"#"
[(set_attr "type" "unary")
@@ -5675,10 +5687,10 @@
[(set (match_operand:DI 0 "register_operand" "")
(zero_extend:DI (plus:SI (plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
(match_operand:SI 2 "arith_operand" ""))
- (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))]
+ (ltu:SI (reg:CC_NOOV ICC_REG) (const_int 0)))))]
"! TARGET_ARCH64 && reload_completed"
[(set (match_dup 3) (plus:SI (plus:SI (match_dup 1) (match_dup 2))
- (ltu:SI (reg:CC_NOOV 100) (const_int 0))))
+ (ltu:SI (reg:CC_NOOV ICC_REG) (const_int 0))))
(set (match_dup 4) (const_int 0))]
"operands[3] = gen_lowpart (SImode, operands[0]);
operands[4] = gen_highpart (SImode, operands[1]);")
@@ -5687,7 +5699,7 @@
[(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI (plus:SI (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
(match_operand:SI 2 "arith_operand" "rI"))
- (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))]
+ (ltu:SI (reg:CC_NOOV ICC_REG) (const_int 0)))))]
"TARGET_ARCH64"
"addx\\t%r1, %2, %0"
[(set_attr "type" "misc")
@@ -5697,7 +5709,7 @@
[(set (match_operand:SI 0 "register_operand" "=r")
(minus:SI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
(match_operand:SI 2 "arith_operand" "rI"))
- (ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
+ (ltu:SI (reg:CC_NOOV ICC_REG) (const_int 0))))]
""
"subx\\t%r1, %2, %0"
[(set_attr "type" "misc")
@@ -5707,7 +5719,7 @@
[(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI (minus:SI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
(match_operand:SI 2 "arith_operand" "rI"))
- (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))]
+ (ltu:SI (reg:CC_NOOV ICC_REG) (const_int 0)))))]
"TARGET_ARCH64"
"subx\\t%r1, %2, %0"
[(set_attr "type" "misc")
@@ -5717,7 +5729,7 @@
[(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI (minus:SI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
(match_operand:SI 2 "arith_operand" "rI"))
- (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))]
+ (ltu:SI (reg:CC_NOOV ICC_REG) (const_int 0)))))]
"! TARGET_ARCH64"
"#"
[(set_attr "type" "unary")
@@ -5727,10 +5739,10 @@
[(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI (minus:SI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
(match_operand:SI 2 "arith_operand" "rI"))
- (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))]
+ (ltu:SI (reg:CC_NOOV ICC_REG) (const_int 0)))))]
"! TARGET_ARCH64 && reload_completed"
[(set (match_dup 3) (minus:SI (minus:SI (match_dup 1) (match_dup 2))
- (ltu:SI (reg:CC_NOOV 100) (const_int 0))))
+ (ltu:SI (reg:CC_NOOV ICC_REG) (const_int 0))))
(set (match_dup 4) (const_int 0))]
"operands[3] = gen_lowpart (SImode, operands[0]);
operands[4] = gen_highpart (SImode, operands[0]);")
@@ -5739,7 +5751,7 @@
[(set (match_operand:DI 0 "register_operand" "=r")
(plus:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
(match_operand:DI 2 "register_operand" "r")))
- (clobber (reg:CC 100))]
+ (clobber (reg:CC ICC_REG))]
"! TARGET_ARCH64"
"#"
[(set_attr "type" "multi")
@@ -5749,15 +5761,15 @@
[(set (match_operand:DI 0 "register_operand" "")
(plus:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
(match_operand:DI 2 "register_operand" "")))
- (clobber (reg:CC 100))]
+ (clobber (reg:CC ICC_REG))]
"! TARGET_ARCH64 && reload_completed"
- [(parallel [(set (reg:CC_NOOV 100)
+ [(parallel [(set (reg:CC_NOOV ICC_REG)
(compare:CC_NOOV (plus:SI (match_dup 3) (match_dup 1))
(const_int 0)))
(set (match_dup 5) (plus:SI (match_dup 3) (match_dup 1)))])
(set (match_dup 6)
(plus:SI (plus:SI (match_dup 4) (const_int 0))
- (ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
+ (ltu:SI (reg:CC_NOOV ICC_REG) (const_int 0))))]
"operands[3] = gen_lowpart (SImode, operands[2]);
operands[4] = gen_highpart (SImode, operands[2]);
operands[5] = gen_lowpart (SImode, operands[0]);
@@ -5804,7 +5816,7 @@
(set_attr "length" "1")])
(define_insn "*cmp_cc_plus"
- [(set (reg:CC_NOOV 100)
+ [(set (reg:CC_NOOV ICC_REG)
(compare:CC_NOOV (plus:SI (match_operand:SI 0 "arith_operand" "%r")
(match_operand:SI 1 "arith_operand" "rI"))
(const_int 0)))]
@@ -5814,7 +5826,7 @@
(set_attr "length" "1")])
(define_insn "*cmp_ccx_plus"
- [(set (reg:CCX_NOOV 100)
+ [(set (reg:CCX_NOOV ICC_REG)
(compare:CCX_NOOV (plus:DI (match_operand:DI 0 "arith_double_operand" "%r")
(match_operand:DI 1 "arith_double_operand" "rHI"))
(const_int 0)))]
@@ -5824,7 +5836,7 @@
(set_attr "length" "1")])
(define_insn "*cmp_cc_plus_set"
- [(set (reg:CC_NOOV 100)
+ [(set (reg:CC_NOOV ICC_REG)
(compare:CC_NOOV (plus:SI (match_operand:SI 1 "arith_operand" "%r")
(match_operand:SI 2 "arith_operand" "rI"))
(const_int 0)))
@@ -5836,7 +5848,7 @@
(set_attr "length" "1")])
(define_insn "*cmp_ccx_plus_set"
- [(set (reg:CCX_NOOV 100)
+ [(set (reg:CCX_NOOV ICC_REG)
(compare:CCX_NOOV (plus:DI (match_operand:DI 1 "arith_double_operand" "%r")
(match_operand:DI 2 "arith_double_operand" "rHI"))
(const_int 0)))
@@ -5877,7 +5889,7 @@
[(set (match_operand:DI 0 "register_operand" "=r")
(minus:DI (match_operand:DI 1 "register_operand" "r")
(match_operand:DI 2 "arith_double_operand" "rHI")))
- (clobber (reg:CC 100))]
+ (clobber (reg:CC ICC_REG))]
"! TARGET_ARCH64"
"#"
[(set_attr "length" "2")])
@@ -5886,7 +5898,7 @@
[(set (match_operand:DI 0 "register_operand" "")
(minus:DI (match_operand:DI 1 "register_operand" "")
(match_operand:DI 2 "arith_double_operand" "")))
- (clobber (reg:CC 100))]
+ (clobber (reg:CC ICC_REG))]
"! TARGET_ARCH64
&& reload_completed
&& (GET_CODE (operands[2]) == CONST_INT
@@ -5923,7 +5935,7 @@
[(set (match_operand:DI 0 "register_operand" "")
(minus:DI (match_operand:DI 1 "register_operand" "")
(match_operand:DI 2 "register_operand" "")))
- (clobber (reg:CC 100))]
+ (clobber (reg:CC ICC_REG))]
"! TARGET_ARCH64
&& reload_completed"
[(clobber (const_int 0))]
@@ -5942,7 +5954,7 @@
[(set (match_operand:DI 0 "register_operand" "=r")
(minus:DI (match_operand:DI 1 "register_operand" "r")
(zero_extend:DI (match_operand:SI 2 "register_operand" "r"))))
- (clobber (reg:CC 100))]
+ (clobber (reg:CC ICC_REG))]
"! TARGET_ARCH64"
"#"
[(set_attr "type" "multi")
@@ -5952,15 +5964,15 @@
[(set (match_operand:DI 0 "register_operand" "")
(minus:DI (match_operand:DI 1 "register_operand" "")
(zero_extend:DI (match_operand:SI 2 "register_operand" ""))))
- (clobber (reg:CC 100))]
+ (clobber (reg:CC ICC_REG))]
"! TARGET_ARCH64 && reload_completed"
- [(parallel [(set (reg:CC_NOOV 100)
+ [(parallel [(set (reg:CC_NOOV ICC_REG)
(compare:CC_NOOV (minus:SI (match_dup 3) (match_dup 2))
(const_int 0)))
(set (match_dup 5) (minus:SI (match_dup 3) (match_dup 2)))])
(set (match_dup 6)
(minus:SI (minus:SI (match_dup 4) (const_int 0))
- (ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
+ (ltu:SI (reg:CC_NOOV ICC_REG) (const_int 0))))]
"operands[3] = gen_lowpart (SImode, operands[1]);
operands[4] = gen_highpart (SImode, operands[1]);
operands[5] = gen_lowpart (SImode, operands[0]);
@@ -6003,7 +6015,7 @@
(set_attr "length" "1")])
(define_insn "*cmp_minus_cc"
- [(set (reg:CC_NOOV 100)
+ [(set (reg:CC_NOOV ICC_REG)
(compare:CC_NOOV (minus:SI (match_operand:SI 0 "reg_or_0_operand" "rJ")
(match_operand:SI 1 "arith_operand" "rI"))
(const_int 0)))]
@@ -6013,7 +6025,7 @@
(set_attr "length" "1")])
(define_insn "*cmp_minus_ccx"
- [(set (reg:CCX_NOOV 100)
+ [(set (reg:CCX_NOOV ICC_REG)
(compare:CCX_NOOV (minus:DI (match_operand:DI 0 "register_operand" "r")
(match_operand:DI 1 "arith_double_operand" "rHI"))
(const_int 0)))]
@@ -6023,7 +6035,7 @@
(set_attr "length" "1")])
(define_insn "cmp_minus_cc_set"
- [(set (reg:CC_NOOV 100)
+ [(set (reg:CC_NOOV ICC_REG)
(compare:CC_NOOV (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
(match_operand:SI 2 "arith_operand" "rI"))
(const_int 0)))
@@ -6035,7 +6047,7 @@
(set_attr "length" "1")])
(define_insn "*cmp_minus_ccx_set"
- [(set (reg:CCX_NOOV 100)
+ [(set (reg:CCX_NOOV ICC_REG)
(compare:CCX_NOOV (minus:DI (match_operand:DI 1 "register_operand" "r")
(match_operand:DI 2 "arith_double_operand" "rHI"))
(const_int 0)))
@@ -6115,7 +6127,7 @@
[(set_attr "length" "9,8")])
(define_insn "*cmp_mul_set"
- [(set (reg:CC 100)
+ [(set (reg:CC ICC_REG)
(compare:CC (mult:SI (match_operand:SI 1 "arith_operand" "%r")
(match_operand:SI 2 "arith_operand" "rI"))
(const_int 0)))
@@ -6555,7 +6567,7 @@
"sdivx\\t%1, %2, %0")
(define_insn "*cmp_sdiv_cc_set"
- [(set (reg:CC 100)
+ [(set (reg:CC ICC_REG)
(compare:CC (div:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "arith_operand" "rI"))
(const_int 0)))
@@ -6620,7 +6632,7 @@
"udivx\\t%1, %2, %0")
(define_insn "*cmp_udiv_cc_set"
- [(set (reg:CC 100)
+ [(set (reg:CC ICC_REG)
(compare:CC (udiv:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "arith_operand" "rI"))
(const_int 0)))
@@ -7077,7 +7089,7 @@
;; want to set the condition code.
(define_insn "*cmp_cc_arith_op"
- [(set (reg:CC 100)
+ [(set (reg:CC ICC_REG)
(compare:CC
(match_operator:SI 2 "cc_arithop"
[(match_operand:SI 0 "arith_operand" "%r")
@@ -7089,7 +7101,7 @@
(set_attr "length" "1")])
(define_insn "*cmp_ccx_arith_op"
- [(set (reg:CCX 100)
+ [(set (reg:CCX ICC_REG)
(compare:CCX
(match_operator:DI 2 "cc_arithop"
[(match_operand:DI 0 "arith_double_operand" "%r")
@@ -7101,7 +7113,7 @@
(set_attr "length" "1")])
(define_insn "*cmp_cc_arith_op_set"
- [(set (reg:CC 100)
+ [(set (reg:CC ICC_REG)
(compare:CC
(match_operator:SI 3 "cc_arithop"
[(match_operand:SI 1 "arith_operand" "%r")
@@ -7115,7 +7127,7 @@
(set_attr "length" "1")])
(define_insn "*cmp_ccx_arith_op_set"
- [(set (reg:CCX 100)
+ [(set (reg:CCX ICC_REG)
(compare:CCX
(match_operator:DI 3 "cc_arithop"
[(match_operand:DI 1 "arith_double_operand" "%r")
@@ -7129,7 +7141,7 @@
(set_attr "length" "1")])
(define_insn "*cmp_cc_xor_not"
- [(set (reg:CC 100)
+ [(set (reg:CC ICC_REG)
(compare:CC
(not:SI (xor:SI (match_operand:SI 0 "reg_or_0_operand" "%rJ")
(match_operand:SI 1 "arith_operand" "rI")))
@@ -7140,7 +7152,7 @@
(set_attr "length" "1")])
(define_insn "*cmp_ccx_xor_not"
- [(set (reg:CCX 100)
+ [(set (reg:CCX ICC_REG)
(compare:CCX
(not:DI (xor:DI (match_operand:DI 0 "reg_or_0_operand" "%rJ")
(match_operand:DI 1 "arith_double_operand" "rHI")))
@@ -7151,7 +7163,7 @@
(set_attr "length" "1")])
(define_insn "*cmp_cc_xor_not_set"
- [(set (reg:CC 100)
+ [(set (reg:CC ICC_REG)
(compare:CC
(not:SI (xor:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
(match_operand:SI 2 "arith_operand" "rI")))
@@ -7164,7 +7176,7 @@
(set_attr "length" "1")])
(define_insn "*cmp_ccx_xor_not_set"
- [(set (reg:CCX 100)
+ [(set (reg:CCX ICC_REG)
(compare:CCX
(not:DI (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
(match_operand:DI 2 "arith_double_operand" "rHI")))
@@ -7177,7 +7189,7 @@
(set_attr "length" "1")])
(define_insn "*cmp_cc_arith_op_not"
- [(set (reg:CC 100)
+ [(set (reg:CC ICC_REG)
(compare:CC
(match_operator:SI 2 "cc_arithopn"
[(not:SI (match_operand:SI 0 "arith_operand" "rI"))
@@ -7189,7 +7201,7 @@
(set_attr "length" "1")])
(define_insn "*cmp_ccx_arith_op_not"
- [(set (reg:CCX 100)
+ [(set (reg:CCX ICC_REG)
(compare:CCX
(match_operator:DI 2 "cc_arithopn"
[(not:DI (match_operand:DI 0 "arith_double_operand" "rHI"))
@@ -7201,7 +7213,7 @@
(set_attr "length" "1")])
(define_insn "*cmp_cc_arith_op_not_set"
- [(set (reg:CC 100)
+ [(set (reg:CC ICC_REG)
(compare:CC
(match_operator:SI 3 "cc_arithopn"
[(not:SI (match_operand:SI 1 "arith_operand" "rI"))
@@ -7216,7 +7228,7 @@
(set_attr "length" "1")])
(define_insn "*cmp_ccx_arith_op_not_set"
- [(set (reg:CCX 100)
+ [(set (reg:CCX ICC_REG)
(compare:CCX
(match_operator:DI 3 "cc_arithopn"
[(not:DI (match_operand:DI 1 "arith_double_operand" "rHI"))
@@ -7256,7 +7268,7 @@
(define_insn "*negdi2_sp32"
[(set (match_operand:DI 0 "register_operand" "=r")
(neg:DI (match_operand:DI 1 "register_operand" "r")))
- (clobber (reg:CC 100))]
+ (clobber (reg:CC ICC_REG))]
"TARGET_ARCH32"
"#"
[(set_attr "type" "unary")
@@ -7265,15 +7277,15 @@
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(neg:DI (match_operand:DI 1 "register_operand" "")))
- (clobber (reg:CC 100))]
+ (clobber (reg:CC ICC_REG))]
"TARGET_ARCH32
&& reload_completed"
- [(parallel [(set (reg:CC_NOOV 100)
+ [(parallel [(set (reg:CC_NOOV ICC_REG)
(compare:CC_NOOV (minus:SI (const_int 0) (match_dup 5))
(const_int 0)))
(set (match_dup 4) (minus:SI (const_int 0) (match_dup 5)))])
(set (match_dup 2) (minus:SI (minus:SI (const_int 0) (match_dup 3))
- (ltu:SI (reg:CC 100) (const_int 0))))]
+ (ltu:SI (reg:CC ICC_REG) (const_int 0))))]
"operands[2] = gen_highpart (SImode, operands[0]);
operands[3] = gen_highpart (SImode, operands[1]);
operands[4] = gen_lowpart (SImode, operands[0]);
@@ -7296,7 +7308,7 @@
(set_attr "length" "1")])
(define_insn "*cmp_cc_neg"
- [(set (reg:CC_NOOV 100)
+ [(set (reg:CC_NOOV ICC_REG)
(compare:CC_NOOV (neg:SI (match_operand:SI 0 "arith_operand" "rI"))
(const_int 0)))]
""
@@ -7305,7 +7317,7 @@
(set_attr "length" "1")])
(define_insn "*cmp_ccx_neg"
- [(set (reg:CCX_NOOV 100)
+ [(set (reg:CCX_NOOV ICC_REG)
(compare:CCX_NOOV (neg:DI (match_operand:DI 0 "arith_double_operand" "rHI"))
(const_int 0)))]
"TARGET_ARCH64"
@@ -7314,7 +7326,7 @@
(set_attr "length" "1")])
(define_insn "*cmp_cc_set_neg"
- [(set (reg:CC_NOOV 100)
+ [(set (reg:CC_NOOV ICC_REG)
(compare:CC_NOOV (neg:SI (match_operand:SI 1 "arith_operand" "rI"))
(const_int 0)))
(set (match_operand:SI 0 "register_operand" "=r")
@@ -7325,7 +7337,7 @@
(set_attr "length" "1")])
(define_insn "*cmp_ccx_set_neg"
- [(set (reg:CCX_NOOV 100)
+ [(set (reg:CCX_NOOV ICC_REG)
(compare:CCX_NOOV (neg:DI (match_operand:DI 1 "arith_double_operand" "rHI"))
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=r")
@@ -7393,7 +7405,7 @@
(set_attr "length" "1,1")])
(define_insn "*cmp_cc_not"
- [(set (reg:CC 100)
+ [(set (reg:CC ICC_REG)
(compare:CC (not:SI (match_operand:SI 0 "arith_operand" "rI"))
(const_int 0)))]
""
@@ -7402,7 +7414,7 @@
(set_attr "length" "1")])
(define_insn "*cmp_ccx_not"
- [(set (reg:CCX 100)
+ [(set (reg:CCX ICC_REG)
(compare:CCX (not:DI (match_operand:DI 0 "arith_double_operand" "rHI"))
(const_int 0)))]
"TARGET_ARCH64"
@@ -7411,7 +7423,7 @@
(set_attr "length" "1")])
(define_insn "*cmp_cc_set_not"
- [(set (reg:CC 100)
+ [(set (reg:CC ICC_REG)
(compare:CC (not:SI (match_operand:SI 1 "arith_operand" "rI"))
(const_int 0)))
(set (match_operand:SI 0 "register_operand" "=r")
@@ -7422,7 +7434,7 @@
(set_attr "length" "1")])
(define_insn "*cmp_ccx_set_not"
- [(set (reg:CCX 100)
+ [(set (reg:CCX ICC_REG)
(compare:CCX (not:DI (match_operand:DI 1 "arith_double_operand" "rHI"))
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=r")
@@ -8130,7 +8142,7 @@
; [(set_attr "length" "4")])
(define_insn "*cmp_cc_ashift_1"
- [(set (reg:CC_NOOV 100)
+ [(set (reg:CC_NOOV ICC_REG)
(compare:CC_NOOV (ashift:SI (match_operand:SI 0 "register_operand" "r")
(const_int 1))
(const_int 0)))]
@@ -8140,7 +8152,7 @@
(set_attr "length" "1")])
(define_insn "*cmp_cc_set_ashift_1"
- [(set (reg:CC_NOOV 100)
+ [(set (reg:CC_NOOV ICC_REG)
(compare:CC_NOOV (ashift:SI (match_operand:SI 1 "register_operand" "r")
(const_int 1))
(const_int 0)))
@@ -8584,7 +8596,7 @@
(define_insn "*call_address_sp32"
[(call (mem:SI (match_operand:SI 0 "address_operand" "p"))
(match_operand 1 "" ""))
- (clobber (reg:SI 15))]
+ (clobber (reg:SI O7_REG))]
;;- Do not use operand 1 for most machines.
"! TARGET_ARCH64"
"call\\t%a0, %1%#"
@@ -8593,7 +8605,7 @@
(define_insn "*call_symbolic_sp32"
[(call (mem:SI (match_operand:SI 0 "symbolic_operand" "s"))
(match_operand 1 "" ""))
- (clobber (reg:SI 15))]
+ (clobber (reg:SI O7_REG))]
;;- Do not use operand 1 for most machines.
"! TARGET_ARCH64"
"call\\t%a0, %1%#"
@@ -8602,7 +8614,7 @@
(define_insn "*call_address_sp64"
[(call (mem:DI (match_operand:DI 0 "address_operand" "p"))
(match_operand 1 "" ""))
- (clobber (reg:DI 15))]
+ (clobber (reg:DI O7_REG))]
;;- Do not use operand 1 for most machines.
"TARGET_ARCH64"
"call\\t%a0, %1%#"
@@ -8611,7 +8623,7 @@
(define_insn "*call_symbolic_sp64"
[(call (mem:DI (match_operand:DI 0 "symbolic_operand" "s"))
(match_operand 1 "" ""))
- (clobber (reg:DI 15))]
+ (clobber (reg:DI O7_REG))]
;;- Do not use operand 1 for most machines.
"TARGET_ARCH64"
"call\\t%a0, %1%#"
@@ -8623,7 +8635,7 @@
[(call (mem:SI (match_operand:SI 0 "address_operand" "p"))
(match_operand 1 "" ""))
(match_operand 2 "immediate_operand" "")
- (clobber (reg:SI 15))]
+ (clobber (reg:SI O7_REG))]
;;- Do not use operand 1 for most machines.
"! TARGET_ARCH64 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 0"
"call\\t%a0, %1\\n\\tnop\\n\\tunimp\\t%2"
@@ -8635,7 +8647,7 @@
[(call (mem:SI (match_operand:SI 0 "symbolic_operand" "s"))
(match_operand 1 "" ""))
(match_operand 2 "immediate_operand" "")
- (clobber (reg:SI 15))]
+ (clobber (reg:SI O7_REG))]
;;- Do not use operand 1 for most machines.
"! TARGET_ARCH64 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 0"
"call\\t%a0, %1\\n\\tnop\\n\\tunimp\\t%2"
@@ -8647,7 +8659,7 @@
[(call (mem:SI (match_operand:SI 0 "address_operand" "p"))
(match_operand 1 "" ""))
(match_operand 2 "immediate_operand" "")
- (clobber (reg:SI 15))]
+ (clobber (reg:SI O7_REG))]
;;- Do not use operand 1 for most machines.
"! TARGET_ARCH64 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0"
"call\\t%a0, %1\\n\\tnop\\n\\tnop"
@@ -8658,7 +8670,7 @@
[(call (mem:SI (match_operand:SI 0 "symbolic_operand" "s"))
(match_operand 1 "" ""))
(match_operand 2 "immediate_operand" "")
- (clobber (reg:SI 15))]
+ (clobber (reg:SI O7_REG))]
;;- Do not use operand 1 for most machines.
"! TARGET_ARCH64 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0"
"call\\t%a0, %1\\n\\tnop\\n\\tnop"
@@ -8706,7 +8718,7 @@
[(set (match_operand 0 "" "=rf")
(call (mem:SI (match_operand:SI 1 "address_operand" "p"))
(match_operand 2 "" "")))
- (clobber (reg:SI 15))]
+ (clobber (reg:SI O7_REG))]
;;- Do not use operand 2 for most machines.
"! TARGET_ARCH64"
"call\\t%a1, %2%#"
@@ -8716,7 +8728,7 @@
[(set (match_operand 0 "" "=rf")
(call (mem:SI (match_operand:SI 1 "symbolic_operand" "s"))
(match_operand 2 "" "")))
- (clobber (reg:SI 15))]
+ (clobber (reg:SI O7_REG))]
;;- Do not use operand 2 for most machines.
"! TARGET_ARCH64"
"call\\t%a1, %2%#"
@@ -8726,7 +8738,7 @@
[(set (match_operand 0 "" "")
(call (mem:DI (match_operand:DI 1 "address_operand" "p"))
(match_operand 2 "" "")))
- (clobber (reg:DI 15))]
+ (clobber (reg:DI O7_REG))]
;;- Do not use operand 2 for most machines.
"TARGET_ARCH64"
"call\\t%a1, %2%#"
@@ -8736,7 +8748,7 @@
[(set (match_operand 0 "" "")
(call (mem:DI (match_operand:DI 1 "symbolic_operand" "s"))
(match_operand 2 "" "")))
- (clobber (reg:DI 15))]
+ (clobber (reg:DI O7_REG))]
;;- Do not use operand 2 for most machines.
"TARGET_ARCH64"
"call\\t%a1, %2%#"
@@ -8828,7 +8840,7 @@
;; all of memory. This blocks insns from being moved across this point.
(define_insn "blockage"
- [(unspec_volatile [(const_int 0)] 0)]
+ [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
""
""
[(set_attr "length" "0")])
@@ -8888,7 +8900,7 @@
(define_insn "return"
[(return)
- (use (reg:SI 31))]
+ (use (reg:SI I7_REG))]
"! TARGET_EPILOGUE"
"* return output_return (operands);"
[(set_attr "type" "return")])
@@ -8897,7 +8909,7 @@
[(set (match_operand:SI 0 "register_operand" "=r")
(match_operand:SI 1 "arith_operand" "rI"))
(parallel [(return)
- (use (reg:SI 31))])]
+ (use (reg:SI I7_REG))])]
"sparc_return_peephole_ok (operands[0], operands[1])"
"return\\t%%i7+8\\n\\tmov\\t%Y1, %Y0")
@@ -8990,14 +9002,14 @@
;; Special trap insn to flush register windows.
(define_insn "flush_register_windows"
- [(unspec_volatile [(const_int 0)] 1)]
+ [(unspec_volatile [(const_int 0)] UNSPECV_FLUSH_REG_WIND)]
""
"* return TARGET_V9 ? \"flushw\" : \"ta\\t3\";"
[(set_attr "type" "misc")
(set_attr "length" "1")])
(define_insn "goto_handler_and_restore"
- [(unspec_volatile [(match_operand 0 "register_operand" "=r")] 2)]
+ [(unspec_volatile [(match_operand 0 "register_operand" "=r")] UNSPECV_GOTO_HANDLER)]
"GET_MODE (operands[0]) == Pmode"
"jmp\\t%0+0\\n\\trestore"
[(set_attr "type" "misc")
@@ -9006,7 +9018,7 @@
;;(define_insn "goto_handler_and_restore_v9"
;; [(unspec_volatile [(match_operand:SI 0 "register_operand" "=r,r")
;; (match_operand:SI 1 "register_operand" "=r,r")
-;; (match_operand:SI 2 "const_int_operand" "I,n")] 3)]
+;; (match_operand:SI 2 "const_int_operand" "I,n")] UNSPECV_GOTO_HANDLER_V9)]
;; "TARGET_V9 && ! TARGET_ARCH64"
;; "@
;; return\\t%0+0\\n\\tmov\\t%2, %Y1
@@ -9017,7 +9029,7 @@
;;(define_insn "*goto_handler_and_restore_v9_sp64"
;; [(unspec_volatile [(match_operand:DI 0 "register_operand" "=r,r")
;; (match_operand:DI 1 "register_operand" "=r,r")
-;; (match_operand:SI 2 "const_int_operand" "I,n")] 3)]
+;; (match_operand:SI 2 "const_int_operand" "I,n")] UNSPECV_GOTO_HANDLER_V9)]
;; "TARGET_V9 && TARGET_ARCH64"
;; "@
;; return\\t%0+0\\n\\tmov\\t%2, %Y1
@@ -9038,7 +9050,7 @@
}")
(define_insn "do_builtin_setjmp_setup"
- [(unspec_volatile [(const_int 0)] 5)]
+ [(unspec_volatile [(const_int 0)] UNSPECV_DO_BUILTIN_SETJMP)]
""
"*
{
@@ -9067,15 +9079,15 @@
}")
(define_expand "setjmp_32"
- [(set (mem:SI (plus:SI (reg:SI 14) (const_int 56))) (match_dup 0))
- (set (mem:SI (plus:SI (reg:SI 14) (const_int 60))) (reg:SI 31))]
+ [(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 56))) (match_dup 0))
+ (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 60))) (reg:SI I7_REG))]
""
"
{ operands[0] = frame_pointer_rtx; }")
(define_expand "setjmp_64"
- [(set (mem:DI (plus:DI (reg:DI 14) (const_int 112))) (match_dup 0))
- (set (mem:DI (plus:DI (reg:DI 14) (const_int 120))) (reg:DI 31))]
+ [(set (mem:DI (plus:DI (reg:DI SP_REG) (const_int 112))) (match_dup 0))
+ (set (mem:DI (plus:DI (reg:DI SP_REG) (const_int 120))) (reg:DI I7_REG))]
""
"
{ operands[0] = frame_pointer_rtx; }")
@@ -9088,13 +9100,13 @@
; it on SImode mem values.
(define_insn "flush"
- [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")] 3)]
+ [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")] UNSPECV_FLUSH)]
""
"* return TARGET_V9 ? \"flush\\t%f0\" : \"iflush\\t%f0\";"
[(set_attr "type" "misc")])
(define_insn "flushdi"
- [(unspec_volatile [(match_operand:DI 0 "memory_operand" "m")] 3)]
+ [(unspec_volatile [(match_operand:DI 0 "memory_operand" "m")] UNSPECV_FLUSH)]
""
"* return TARGET_V9 ? \"flush\\t%f0\" : \"iflush\\t%f0\";"
[(set_attr "type" "misc")])
@@ -9260,7 +9272,7 @@
(define_peephole
[(set (match_operand:SI 0 "register_operand" "=r")
(match_operand:SI 1 "register_operand" "r"))
- (set (reg:CC 100)
+ (set (reg:CC ICC_REG)
(compare:CC (match_operand:SI 2 "register_operand" "r")
(const_int 0)))]
"(rtx_equal_p (operands[2], operands[0])
@@ -9272,7 +9284,7 @@
(define_peephole
[(set (match_operand:DI 0 "register_operand" "=r")
(match_operand:DI 1 "register_operand" "r"))
- (set (reg:CCX 100)
+ (set (reg:CCX ICC_REG)
(compare:CCX (match_operand:DI 2 "register_operand" "r")
(const_int 0)))]
"TARGET_ARCH64
@@ -9437,7 +9449,7 @@
;; The following pattern is only generated by delayed-branch scheduling,
;; when the insn winds up in the epilogue.
(define_insn "*return_sf"
- [(set (reg:SF 32)
+ [(set (reg:SF F0_REG)
(match_operand:SF 0 "register_operand" "f"))
(return)]
"! TARGET_EPILOGUE"
@@ -9450,7 +9462,7 @@
[(parallel [(set (match_operand 0 "" "")
(call (mem:SI (match_operand:SI 1 "call_operand_address" "ps"))
(match_operand 2 "" "")))
- (clobber (reg:SI 15))])
+ (clobber (reg:SI O7_REG))])
(set (pc) (label_ref (match_operand 3 "" "")))]
"short_branch (INSN_UID (insn), INSN_UID (operands[3]))
&& in_same_eh_region (insn, operands[3])
@@ -9460,7 +9472,7 @@
(define_peephole
[(parallel [(call (mem:SI (match_operand:SI 0 "call_operand_address" "ps"))
(match_operand 1 "" ""))
- (clobber (reg:SI 15))])
+ (clobber (reg:SI O7_REG))])
(set (pc) (label_ref (match_operand 2 "" "")))]
"short_branch (INSN_UID (insn), INSN_UID (operands[2]))
&& in_same_eh_region (insn, operands[2])
@@ -9471,7 +9483,7 @@
[(parallel [(set (match_operand 0 "" "")
(call (mem:SI (match_operand:DI 1 "call_operand_address" "ps"))
(match_operand 2 "" "")))
- (clobber (reg:DI 15))])
+ (clobber (reg:DI O7_REG))])
(set (pc) (label_ref (match_operand 3 "" "")))]
"TARGET_ARCH64
&& short_branch (INSN_UID (insn), INSN_UID (operands[3]))
@@ -9482,7 +9494,7 @@
(define_peephole
[(parallel [(call (mem:SI (match_operand:DI 0 "call_operand_address" "ps"))
(match_operand 1 "" ""))
- (clobber (reg:DI 15))])
+ (clobber (reg:DI O7_REG))])
(set (pc) (label_ref (match_operand 2 "" "")))]
"TARGET_ARCH64
&& short_branch (INSN_UID (insn), INSN_UID (operands[2]))
@@ -9538,7 +9550,7 @@
operands[3] = const0_rtx;")
(define_insn ""
- [(trap_if (match_operator 0 "noov_compare_op" [(reg:CC 100) (const_int 0)])
+ [(trap_if (match_operator 0 "noov_compare_op" [(reg:CC ICC_REG) (const_int 0)])
(match_operand:SI 1 "arith_operand" "rM"))]
""
"t%C0\\t%1"
@@ -9546,7 +9558,7 @@
(set_attr "length" "1")])
(define_insn ""
- [(trap_if (match_operator 0 "noov_compare_op" [(reg:CCX 100) (const_int 0)])
+ [(trap_if (match_operator 0 "noov_compare_op" [(reg:CCX ICC_REG) (const_int 0)])
(match_operand:SI 1 "arith_operand" "rM"))]
"TARGET_V9"
"t%C0\\t%%xcc, %1"