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Mips warning cleanup
- To: gcc-patches at gcc dot gnu dot org
- Subject: Mips warning cleanup
- From: Michael Meissner <meissner at redhat dot com>
- Date: Fri, 16 Mar 2001 13:12:08 -0500
The following patch cleans up some warnings that the MIPS port was
getting due to warnings about differences between constants with the
high bit set between traditional C and ISO C. I checked the MIPS port
by doing a build. At present, I've only checked this into the
mainline, but can check it into the 3.0 branch if desired.
2001-03-16 Michael Meissner <meissner@redhat.com>
* mips.h (BITMASK_HIGH): Replacement for 0x80000000 that avoids
warnings.
(BITMASK_UPPER16): Replacement for 0xffff0000 that avoids
warnings.
(BITMASK_LOWER16): Replacement for 0x0000ffff.
* mips.c (save_restore_insns): Use BITMASK_UPPER16/BITMASK_LOWER16
instead of 0xffff0000/0x0000ffff to avoid warnings about constants
being unsigned in ISO C and signed in traditional.
(expand_prologue): Ditto.
(RA_MASK): Use BITMASK_HIGH to avoid warnings.
* mips.md (divmodsi4,divmodsi4): Use BITMASK_HIGH to avoid
warnings.
(divsi3,divdi3): Ditto.
(modsi3,moddi3): Ditto.
(fix_truncdfsi2,fix_truncdfdi2): Ditto.
(fix_truncsfsi2,fix_truncsfdi2): Ditto.
(movsi split): Use BITMASK_UPPER16/BITMASK_LOWER16 to avoid
warnings.
*** gcc/config/mips/mips.h.~1~ Fri Mar 16 12:06:17 2001
--- gcc/config/mips/mips.h Fri Mar 16 12:57:10 2001
*************** extern void sbss_section PARAMS ((void)
*** 179,184 ****
--- 179,191 ----
#define HALF_PIC_FINISH(STREAM)
#endif
+ /* Macros to silence warnings about numbers being signed in traditional
+ C and unsigned in ISO C when compiled on 32-bit hosts. */
+
+ #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
+ #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
+ #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
+
/* Run-time compilation parameters selecting different hardware subsets. */
*** gcc/config/mips/mips.c.~1~ Fri Mar 16 12:06:17 2001
--- gcc/config/mips/mips.c Fri Mar 16 12:27:04 2001
*************** save_restore_insns (store_p, large_reg,
*** 6452,6463 ****
&& GET_MODE (base_reg_rtx) == SImode)
{
insn = emit_move_insn (base_reg_rtx,
! GEN_INT (gp_offset & 0xffff0000));
if (store_p)
RTX_FRAME_RELATED_P (insn) = 1;
insn
= emit_insn (gen_iorsi3 (base_reg_rtx, base_reg_rtx,
! GEN_INT (gp_offset & 0x0000ffff)));
if (store_p)
RTX_FRAME_RELATED_P (insn) = 1;
}
--- 6452,6464 ----
&& GET_MODE (base_reg_rtx) == SImode)
{
insn = emit_move_insn (base_reg_rtx,
! GEN_INT (gp_offset & BITMASK_UPPER16));
if (store_p)
RTX_FRAME_RELATED_P (insn) = 1;
insn
= emit_insn (gen_iorsi3 (base_reg_rtx, base_reg_rtx,
! GEN_INT (gp_offset
! & BITMASK_LOWER16)));
if (store_p)
RTX_FRAME_RELATED_P (insn) = 1;
}
*************** save_restore_insns (store_p, large_reg,
*** 6671,6681 ****
&& GET_MODE (base_reg_rtx) == SImode)
{
insn = emit_move_insn (base_reg_rtx,
! GEN_INT (fp_offset & 0xffff0000));
if (store_p)
RTX_FRAME_RELATED_P (insn) = 1;
insn = emit_insn (gen_iorsi3 (base_reg_rtx, base_reg_rtx,
! GEN_INT (fp_offset & 0x0000ffff)));
if (store_p)
RTX_FRAME_RELATED_P (insn) = 1;
}
--- 6672,6683 ----
&& GET_MODE (base_reg_rtx) == SImode)
{
insn = emit_move_insn (base_reg_rtx,
! GEN_INT (fp_offset & BITMASK_UPPER16));
if (store_p)
RTX_FRAME_RELATED_P (insn) = 1;
insn = emit_insn (gen_iorsi3 (base_reg_rtx, base_reg_rtx,
! GEN_INT (fp_offset
! & BITMASK_LOWER16)));
if (store_p)
RTX_FRAME_RELATED_P (insn) = 1;
}
*************** mips_expand_prologue ()
*** 7223,7232 ****
&& GET_MODE (tmp_rtx) == SImode)
{
insn = emit_move_insn (tmp_rtx,
! GEN_INT (tsize & 0xffff0000));
RTX_FRAME_RELATED_P (insn) = 1;
insn = emit_insn (gen_iorsi3 (tmp_rtx, tmp_rtx,
! GEN_INT (tsize & 0x0000ffff)));
RTX_FRAME_RELATED_P (insn) = 1;
}
else
--- 7225,7235 ----
&& GET_MODE (tmp_rtx) == SImode)
{
insn = emit_move_insn (tmp_rtx,
! GEN_INT (tsize & BITMASK_UPPER16));
RTX_FRAME_RELATED_P (insn) = 1;
insn = emit_insn (gen_iorsi3 (tmp_rtx, tmp_rtx,
! GEN_INT (tsize
! & BITMASK_LOWER16)));
RTX_FRAME_RELATED_P (insn) = 1;
}
else
*************** mips_expand_prologue ()
*** 7342,7348 ****
/* Do any necessary cleanup after a function to restore stack, frame,
and regs. */
! #define RA_MASK 0x80000000L /* 1 << 31 */
#define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
void
--- 7345,7351 ----
/* Do any necessary cleanup after a function to restore stack, frame,
and regs. */
! #define RA_MASK BITMASK_HIGH /* 1 << 31 */
#define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
void
*** gcc/config/mips/mips.md.~1~ Fri Mar 16 12:06:17 2001
--- gcc/config/mips/mips.md Fri Mar 16 12:19:34 2001
***************
*** 2277,2283 ****
copy_to_mode_reg (SImode, GEN_INT (-1)),
GEN_INT (0x6)));
emit_insn (gen_div_trap (operands[2],
! copy_to_mode_reg (SImode, GEN_INT (0x80000000)),
GEN_INT (0x6)));
}
--- 2277,2283 ----
copy_to_mode_reg (SImode, GEN_INT (-1)),
GEN_INT (0x6)));
emit_insn (gen_div_trap (operands[2],
! copy_to_mode_reg (SImode, GEN_INT (BITMASK_HIGH)),
GEN_INT (0x6)));
}
***************
*** 2324,2330 ****
copy_to_mode_reg (DImode, GEN_INT (-1)),
GEN_INT (0x6)));
emit_insn (gen_div_trap (operands[2],
! copy_to_mode_reg (DImode, GEN_INT (0x80000000)),
GEN_INT (0x6)));
}
--- 2324,2330 ----
copy_to_mode_reg (DImode, GEN_INT (-1)),
GEN_INT (0x6)));
emit_insn (gen_div_trap (operands[2],
! copy_to_mode_reg (DImode, GEN_INT (BITMASK_HIGH)),
GEN_INT (0x6)));
}
***************
*** 2535,2541 ****
copy_to_mode_reg (SImode, GEN_INT (-1)),
GEN_INT (0x6)));
emit_insn (gen_div_trap (operands[2],
! copy_to_mode_reg (SImode, GEN_INT (0x80000000)),
GEN_INT (0x6)));
}
--- 2535,2541 ----
copy_to_mode_reg (SImode, GEN_INT (-1)),
GEN_INT (0x6)));
emit_insn (gen_div_trap (operands[2],
! copy_to_mode_reg (SImode, GEN_INT (BITMASK_HIGH)),
GEN_INT (0x6)));
}
***************
*** 2575,2581 ****
copy_to_mode_reg (DImode, GEN_INT (-1)),
GEN_INT (0x6)));
emit_insn (gen_div_trap (operands[2],
! copy_to_mode_reg (DImode, GEN_INT (0x80000000)),
GEN_INT (0x6)));
}
--- 2575,2581 ----
copy_to_mode_reg (DImode, GEN_INT (-1)),
GEN_INT (0x6)));
emit_insn (gen_div_trap (operands[2],
! copy_to_mode_reg (DImode, GEN_INT (BITMASK_HIGH)),
GEN_INT (0x6)));
}
***************
*** 2615,2621 ****
copy_to_mode_reg (SImode, GEN_INT (-1)),
GEN_INT (0x6)));
emit_insn (gen_div_trap (operands[2],
! copy_to_mode_reg (SImode, GEN_INT (0x80000000)),
GEN_INT (0x6)));
}
--- 2615,2621 ----
copy_to_mode_reg (SImode, GEN_INT (-1)),
GEN_INT (0x6)));
emit_insn (gen_div_trap (operands[2],
! copy_to_mode_reg (SImode, GEN_INT (BITMASK_HIGH)),
GEN_INT (0x6)));
}
***************
*** 2655,2661 ****
copy_to_mode_reg (DImode, GEN_INT (-1)),
GEN_INT (0x6)));
emit_insn (gen_div_trap (operands[2],
! copy_to_mode_reg (DImode, GEN_INT (0x80000000)),
GEN_INT (0x6)));
}
--- 2655,2661 ----
copy_to_mode_reg (DImode, GEN_INT (-1)),
GEN_INT (0x6)));
emit_insn (gen_div_trap (operands[2],
! copy_to_mode_reg (DImode, GEN_INT (BITMASK_HIGH)),
GEN_INT (0x6)));
}
*************** move\\t%0,%z4\\n\\
*** 4319,4325 ****
emit_label (label1);
emit_move_insn (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
! emit_move_insn (reg3, GEN_INT (0x80000000));
emit_insn (gen_fix_truncdfsi2 (operands[0], reg2));
emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
--- 4319,4325 ----
emit_label (label1);
emit_move_insn (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
! emit_move_insn (reg3, GEN_INT (BITMASK_HIGH));
emit_insn (gen_fix_truncdfsi2 (operands[0], reg2));
emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
*************** move\\t%0,%z4\\n\\
*** 4362,4368 ****
emit_label (label1);
emit_move_insn (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
! emit_move_insn (reg3, GEN_INT (0x80000000));
emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
emit_insn (gen_fix_truncdfdi2 (operands[0], reg2));
--- 4362,4368 ----
emit_label (label1);
emit_move_insn (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
! emit_move_insn (reg3, GEN_INT (BITMASK_HIGH));
emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
emit_insn (gen_fix_truncdfdi2 (operands[0], reg2));
*************** move\\t%0,%z4\\n\\
*** 4406,4412 ****
emit_label (label1);
emit_move_insn (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
! emit_move_insn (reg3, GEN_INT (0x80000000));
emit_insn (gen_fix_truncsfsi2 (operands[0], reg2));
emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
--- 4406,4412 ----
emit_label (label1);
emit_move_insn (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
! emit_move_insn (reg3, GEN_INT (BITMASK_HIGH));
emit_insn (gen_fix_truncsfsi2 (operands[0], reg2));
emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
*************** move\\t%0,%z4\\n\\
*** 4449,4455 ****
emit_label (label1);
emit_move_insn (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
! emit_move_insn (reg3, GEN_INT (0x80000000));
emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
emit_insn (gen_fix_truncsfdi2 (operands[0], reg2));
--- 4449,4455 ----
emit_label (label1);
emit_move_insn (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
! emit_move_insn (reg3, GEN_INT (BITMASK_HIGH));
emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
emit_insn (gen_fix_truncsfdi2 (operands[0], reg2));
*************** move\\t%0,%z4\\n\\
*** 5179,5186 ****
(match_dup 3)))]
"
{
! operands[2] = GEN_INT (INTVAL (operands[1]) & 0xffff0000);
! operands[3] = GEN_INT (INTVAL (operands[1]) & 0x0000ffff);
}")
;; Unlike most other insns, the move insns can't be split with
--- 5179,5186 ----
(match_dup 3)))]
"
{
! operands[2] = GEN_INT (INTVAL (operands[1]) & BITMASK_UPPER16);
! operands[3] = GEN_INT (INTVAL (operands[1]) & BITMASK_LOWER16);
}")
;; Unlike most other insns, the move insns can't be split with
--
Michael Meissner, Red Hat, Inc. (GCC group)
PMB 198, 174 Littleton Road #3, Westford, Massachusetts 01886, USA
Work: meissner@redhat.com phone: +1 978-486-9304
Non-work: meissner@spectacle-pond.org fax: +1 978-692-4482