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SSE logical patterns


Hi,
This patch adds patterns to distinguish all three types of SSE and - packed
float/double precision and integer.

This is done using subregs, since generic code don't expect logicals on floats.
I am emitting those patterns only after reload by splitting abs/cmove patterns,
so this should be OK. Even they should survive reload well, since the subregs
are eliminated only inside arugments, so the builtins can use them - we will
need to add packed mode versions.

Honza

Tue Feb 27 13:24:46 CET 2001  Jan Hubicka  <jh@suse.cz>

	* i386.md (sse_andti3, sse_nandti_3, sse_xorti3): Add SSE2 versions;
	add missing '%' in constraints.


Index: i386.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/i386/i386.md,v
retrieving revision 1.218
diff -c -3 -p -r1.218 i386.md
*** i386.md	2001/02/21 18:20:17	1.218
--- i386.md	2001/02/27 12:21:50
***************
*** 13607,13644 ****
  ;; into DImode subregs of SSE registers, and them together, and move out
  ;; of DImode subregs again!
  
  (define_insn "sse_andti3"
    [(set (match_operand:TI 0 "register_operand" "=x")
!         (and:TI (match_operand:TI 1 "register_operand" "0")
  		(match_operand:TI 2 "nonimmediate_operand" "xm")))]
!   "TARGET_SSE"
    "andps\\t{%2, %0|%0, %2}"
    [(set_attr "type" "sse")])
  
  (define_insn "sse_nandti3"
    [(set (match_operand:TI 0 "register_operand" "=x")
          (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
  		(match_operand:TI 2 "nonimmediate_operand" "xm")))]
!   "TARGET_SSE"
    "andnps\\t{%2, %0|%0, %2}"
    [(set_attr "type" "sse")])
  
  (define_insn "sse_iorti3"
    [(set (match_operand:TI 0 "register_operand" "=x")
!         (ior:TI (match_operand:TI 1 "register_operand" "0")
  		(match_operand:TI 2 "nonimmediate_operand" "xm")))]
    "TARGET_SSE"
!   "iorps\\t{%2, %0|%0, %2}"
    [(set_attr "type" "sse")])
  
  (define_insn "sse_xorti3"
    [(set (match_operand:TI 0 "register_operand" "=x")
!         (xor:TI (match_operand:TI 1 "register_operand" "0")
  		(match_operand:TI 2 "nonimmediate_operand" "xm")))]
!   "TARGET_SSE"
    "xorps\\t{%2, %0|%0, %2}"
    [(set_attr "type" "sse")])
  
  ;; Use xor, but don't show input operands so they aren't live before
  ;; this insn.
  (define_insn "sse_clrti"
--- 14256,14437 ----
  ;; into DImode subregs of SSE registers, and them together, and move out
  ;; of DImode subregs again!
  
+ (define_insn "*sse_andti3_df_1"
+   [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
+         (and:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0)
+ 		(subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
+   "TARGET_SSE2"
+   "andpd\\t{%2, %0|%0, %2}"
+   [(set_attr "type" "sse")])
+ 
+ (define_insn "*sse_andti3_df_2"
+   [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
+         (and:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0)
+ 		(match_operand:TI 2 "nonimmediate_operand" "Ym")))]
+   "TARGET_SSE2"
+   "andpd\\t{%2, %0|%0, %2}"
+   [(set_attr "type" "sse")])
+ 
+ (define_insn "*sse_andti3_sf_1"
+   [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
+         (and:TI (subreg:TI (match_operand:SF 1 "register_operand" "%0") 0)
+ 		(subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
+   "TARGET_SSE"
+   "andps\\t{%2, %0|%0, %2}"
+   [(set_attr "type" "sse")])
+ 
+ (define_insn "*sse_andti3_sf_2"
+   [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
+         (and:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
+ 		(match_operand:TI 2 "nonimmediate_operand" "xm")))]
+   "TARGET_SSE"
+   "andps\\t{%2, %0|%0, %2}"
+   [(set_attr "type" "sse")])
+ 
  (define_insn "sse_andti3"
    [(set (match_operand:TI 0 "register_operand" "=x")
!         (and:TI (match_operand:TI 1 "register_operand" "%0")
  		(match_operand:TI 2 "nonimmediate_operand" "xm")))]
!   "TARGET_SSE && !TARGET_SSE2"
    "andps\\t{%2, %0|%0, %2}"
    [(set_attr "type" "sse")])
  
+ (define_insn "*sse_andti3_sse2"
+   [(set (match_operand:TI 0 "register_operand" "=x")
+         (and:TI (match_operand:TI 1 "register_operand" "%0")
+ 		(match_operand:TI 2 "nonimmediate_operand" "xm")))]
+   "TARGET_SSE2"
+   "pand\\t{%2, %0|%0, %2}"
+   [(set_attr "type" "sse")])
+ 
+ (define_insn "*sse_nandti3_df"
+   [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
+         (and:TI (not:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0))
+ 		(match_operand:TI 2 "nonimmediate_operand" "Ym")))]
+   "TARGET_SSE2"
+   "andnpd\\t{%2, %0|%0, %2}"
+   [(set_attr "type" "sse")])
+ 
+ (define_insn "*sse_nandti3_sf"
+   [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
+         (and:TI (not:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0))
+ 		(match_operand:TI 2 "nonimmediate_operand" "xm")))]
+   "TARGET_SSE"
+   "andnps\\t{%2, %0|%0, %2}"
+   [(set_attr "type" "sse")])
+ 
  (define_insn "sse_nandti3"
    [(set (match_operand:TI 0 "register_operand" "=x")
          (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
  		(match_operand:TI 2 "nonimmediate_operand" "xm")))]
!   "TARGET_SSE && !TARGET_SSE2"
    "andnps\\t{%2, %0|%0, %2}"
    [(set_attr "type" "sse")])
  
+ (define_insn "*sse_nandti3_sse2"
+   [(set (match_operand:TI 0 "register_operand" "=x")
+         (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
+ 		(match_operand:TI 2 "nonimmediate_operand" "xm")))]
+   "TARGET_SSE2"
+   "pnand\\t{%2, %0|%0, %2}"
+   [(set_attr "type" "sse")])
+ 
+ (define_insn "*sse_iorti3_df_1"
+   [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
+         (ior:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0)
+ 		(subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
+   "TARGET_SSE2"
+   "orpd\\t{%2, %0|%0, %2}"
+   [(set_attr "type" "sse")])
+ 
+ (define_insn "*sse_iorti3_df_2"
+   [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
+         (ior:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0)
+ 		(match_operand:TI 2 "nonimmediate_operand" "Ym")))]
+   "TARGET_SSE2"
+   "orpd\\t{%2, %0|%0, %2}"
+   [(set_attr "type" "sse")])
+ 
+ (define_insn "*sse_iorti3_sf_1"
+   [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
+         (ior:TI (subreg:TI (match_operand:SF 1 "register_operand" "%0") 0)
+ 		(subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
+   "TARGET_SSE"
+   "orps\\t{%2, %0|%0, %2}"
+   [(set_attr "type" "sse")])
+ 
+ (define_insn "*sse_iorti3_sf_2"
+   [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
+         (ior:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
+ 		(match_operand:TI 2 "nonimmediate_operand" "xm")))]
+   "TARGET_SSE"
+   "orps\\t{%2, %0|%0, %2}"
+   [(set_attr "type" "sse")])
+ 
  (define_insn "sse_iorti3"
+   [(set (match_operand:TI 0 "register_operand" "=x")
+         (ior:TI (match_operand:TI 1 "register_operand" "%0")
+ 		(match_operand:TI 2 "nonimmediate_operand" "xm")))]
+   "TARGET_SSE && !TARGET_SSE2"
+   "orps\\t{%2, %0|%0, %2}"
+   [(set_attr "type" "sse")])
+ 
+ (define_insn "*sse_iorti3_sse2"
    [(set (match_operand:TI 0 "register_operand" "=x")
!         (ior:TI (match_operand:TI 1 "register_operand" "%0")
  		(match_operand:TI 2 "nonimmediate_operand" "xm")))]
+   "TARGET_SSE2"
+   "por\\t{%2, %0|%0, %2}"
+   [(set_attr "type" "sse")])
+ 
+ (define_insn "*sse_xorti3_df_1"
+   [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
+         (xor:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0)
+ 		(subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
+   "TARGET_SSE2"
+   "xorpd\\t{%2, %0|%0, %2}"
+   [(set_attr "type" "sse")])
+ 
+ (define_insn "*sse_xorti3_df_2"
+   [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
+         (xor:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0)
+ 		(match_operand:TI 2 "nonimmediate_operand" "Ym")))]
+   "TARGET_SSE2"
+   "xorpd\\t{%2, %0|%0, %2}"
+   [(set_attr "type" "sse")])
+ 
+ (define_insn "*sse_xorti3_sf_1"
+   [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
+         (xor:TI (subreg:TI (match_operand:SF 1 "register_operand" "%0") 0)
+ 		(subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
    "TARGET_SSE"
!   "xorps\\t{%2, %0|%0, %2}"
    [(set_attr "type" "sse")])
  
+ (define_insn "*sse_xorti3_sf_2"
+   [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
+         (xor:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
+ 		(match_operand:TI 2 "nonimmediate_operand" "xm")))]
+   "TARGET_SSE"
+   "xorps\\t{%2, %0|%0, %2}"
+   [(set_attr "type" "sse")])
+ 
  (define_insn "sse_xorti3"
    [(set (match_operand:TI 0 "register_operand" "=x")
!         (xor:TI (match_operand:TI 1 "register_operand" "%0")
  		(match_operand:TI 2 "nonimmediate_operand" "xm")))]
!   "TARGET_SSE && !TARGET_SSE2"
    "xorps\\t{%2, %0|%0, %2}"
    [(set_attr "type" "sse")])
  
+ (define_insn "*sse_xorti3_sse2"
+   [(set (match_operand:TI 0 "register_operand" "=x")
+         (xor:TI (match_operand:TI 1 "register_operand" "%0")
+ 		(match_operand:TI 2 "nonimmediate_operand" "xm")))]
+   "TARGET_SSE2"
+   "pxor\\t{%2, %0|%0, %2}"
+   [(set_attr "type" "sse")])
+ 
  ;; Use xor, but don't show input operands so they aren't live before
  ;; this insn.
  (define_insn "sse_clrti"


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