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Re: [patches] Re: SSE min/max instruction support

To: Richard Henderson <rth at redhat dot com>, Jan Hubicka <jh at suse dot cz>, gcc-patches at gcc dot gnu dot org, patches at x86-64 dot org
Subject: Re: [patches] Re: SSE min/max instruction support
From: Jan Hubicka <jh at suse dot cz>
Date: Sun, 25 Feb 2001 00:33:45 +0100
References: <20010224022013.L7388@atrey.karlin.mff.cuni.cz> <20010224125539.A4181@redhat.com> <20010224233442.A26961@atrey.karlin.mff.cuni.cz> <20010224143739.A4359@redhat.com> <20010225001414.E26961@atrey.karlin.mff.cuni.cz> <20010224152125.B4379@redhat.com>

OK, I am investigating ifcvt.c - proper place seems to be noce_emit_cmove.
In order to do canonicalization, I should know about constantness of the
operands. On RISC architectures I don't think I see it - do you see
as good solution to call init_alias_analysis and canon_exp on the
operands before doing the simplifications?

Honza

Follow-Ups:
- Re: [patches] Re: SSE min/max instruction support
  - From: Richard Henderson

References:
- SSE min/max instruction support
  - From: Jan Hubicka
- Re: SSE min/max instruction support
  - From: Richard Henderson
- Re: [patches] Re: SSE min/max instruction support
  - From: Jan Hubicka
- Re: [patches] Re: SSE min/max instruction support
  - From: Richard Henderson
- Re: [patches] Re: SSE min/max instruction support
  - From: Jan Hubicka
- Re: [patches] Re: SSE min/max instruction support
  - From: Richard Henderson

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