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Tiny SSE tweeks


Hi
This patch adds two simple tweeks to SSE code.  First one makes gcc to amit
movaps instead of movss and movapd instead of movsd on CPUs with partial
register dependencies.  This helps quite a lot on P4.

Second change if to truncdfsf patterns to avoid gcc from doing truncations
SSE register -> memory
as SSE register -> FP register -> memory
but as SSE register -> SSE register -> memory

Honza

Sat Feb 24 02:32:31 CET 2001  Jan Hubicka  <jh@suse.cz>

	* i386.md (movsf, movdf): Use movaps for reg-reg moves if
	TARGET_PARTIAL_REG_DEPENDENCY.
	(truncdfsf2_1_sse, truncdfsf2_2): Penalize the fpreg->mem case.

*** /p1/x86-64/egcs/gcc/config/i386/i386.md	Fri Feb 16 18:34:23 2001
--- i386.md	Sat Feb 24 02:23:59 2001
***************
*** 2238,2243 ****
--- 2238,2247 ----
        return \"mov{l}\\t{%1, %0|%0, %1}\";
      case 5:
      case 6:
+       if (TARGET_PARTIAL_REG_DEPENDENCY
+ 	  && register_operand (operands[0], VOIDmode)
+ 	  && register_operand (operands[1], VOIDmode))
+ 	return \"movaps\\t{%1, %0|%0, %1}\";
        return \"movss\\t{%1, %0|%0, %1}\";
  
      default:
***************
*** 2412,2417 ****
--- 2416,2425 ----
        return \"#\";
      case 5:
      case 6:
+       if (TARGET_PARTIAL_REG_DEPENDENCY
+ 	  && register_operand (operands[0], VOIDmode)
+ 	  && register_operand (operands[1], VOIDmode))
+ 	return \"movapd\\t{%1, %0|%0, %1}\";
        return \"movsd\\t{%1, %0|%0, %1}\";
  
      default:
***************
*** 3626,3632 ****
     (set_attr "mode" "SF,SF")])
  
  (define_insn "*truncdfsf2_1_sse"
!   [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f,Y")
  	(float_truncate:SF
  	 (match_operand:DF 1 "nonimmediate_operand" "f,0,mY")))
     (clobber (match_operand:SF 2 "memory_operand" "=X,m,X"))]
--- 3634,3640 ----
     (set_attr "mode" "SF,SF")])
  
  (define_insn "*truncdfsf2_1_sse"
!   [(set (match_operand:SF 0 "nonimmediate_operand" "=*!m,?f,Y")
  	(float_truncate:SF
  	 (match_operand:DF 1 "nonimmediate_operand" "f,0,mY")))
     (clobber (match_operand:SF 2 "memory_operand" "=X,m,X"))]
***************
*** 3652,3677 ****
     (set_attr "mode" "SF,SF,DF")])
  
  (define_insn "*truncdfsf2_2"
!   [(set (match_operand:SF 0 "nonimmediate_operand" "=m,Y")
  	(float_truncate:SF
! 	 (match_operand:DF 1 "nonimmediate_operand" "f,mY")))]
!   "TARGET_80387 && TARGET_SSE2"
    "*
  {
    switch (which_alternative)
      {
      case 0:
        if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
  	return \"fstp%z0\\t%y0\";
        else
  	return \"fst%z0\\t%y0\";
-     case 1:
-     case 2:
-       return \"cvtsd2ss\\t{%1, %0|%0, %1}\";
      }
  }"
!   [(set_attr "type" "fmov,sse")
!    (set_attr "mode" "SF,DF")])
  
  (define_insn "truncdfsf2_3"
    [(set (match_operand:SF 0 "nonimmediate_operand" "=m")
--- 3660,3685 ----
     (set_attr "mode" "SF,SF,DF")])
  
  (define_insn "*truncdfsf2_2"
!   [(set (match_operand:SF 0 "nonimmediate_operand" "=Y,!m")
  	(float_truncate:SF
! 	 (match_operand:DF 1 "nonimmediate_operand" "mY,f")))]
!   "TARGET_80387 && TARGET_SSE2
!    && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
    "*
  {
    switch (which_alternative)
      {
      case 0:
+       return \"cvtsd2ss\\t{%1, %0|%0, %1}\";
+     case 1:
        if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
  	return \"fstp%z0\\t%y0\";
        else
  	return \"fst%z0\\t%y0\";
      }
  }"
!   [(set_attr "type" "sse,fmov")
!    (set_attr "mode" "DF,SF")])
  
  (define_insn "truncdfsf2_3"
    [(set (match_operand:SF 0 "nonimmediate_operand" "=m")


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