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Re: [PATCH] Re: REG_DEAD/REG_EQUIV problem.


Following up on this,

> Executing on host: /xxx/gnu/gcc-2.97/objdir/gcc/xgcc -B/xxx/gnu/gcc-2.97/objdir/gcc/ /xxx/gnu/gcc-2.97/gcc/testsuite/gcc.c-torture/compile/900313-1.c  -w  -O0 -c  -fPIC -o /xxx/gnu/gcc-2.97/objdir/gcc/testsuite/900313-1.o    (timeout = -1)
> /xxx/gnu/gcc-2.97/gcc/testsuite/gcc.c-torture/compile/900313-1.c: In function `main':
> /xxx/gnu/gcc-2.97/gcc/testsuite/gcc.c-torture/compile/900313-1.c:7: Insn does not satisfy its constraints:
> (insn 104 55 107 (set (reg:SI 111)
> 	(reg:SI 1 %r1)) 69 {*pa.md:2099} (nil)
>     (nil))
> /xxx/gnu/gcc-2.97/gcc/testsuite/gcc.c-torture/compile/900313-1.c:7: confused by earlier errors, bailing out

it appears that reload is behaving rather strangely.  The following test
program will trigger the fault:

main ()
{
  alloca ((int) &main);;
}

Here is the crucial rtl from lreg:

(insn 13 8 15 (set (reg:SI 97)
        (plus:SI (reg:SI 19 %r19)
            (high:SI (symbol_ref/u:SI ("*L$C0000"))))) 80 {*pa.md:2326} (nil)
    (nil))

(insn 15 13 16 (set (reg:SI 97)
        (mem:SI (lo_sum:SI (reg:SI 97)
                (unspec:SI[ 
                        (symbol_ref/u:SI ("*L$C0000"))
                    ]  0)) 0)) 82 {*pa.md:2352} (nil)
    (nil))

(insn 16 15 18 (set (reg:SI 96)
        (reg:SI 97)) 69 {*pa.md:2099} (nil)
    (expr_list:REG_DEAD (reg:SI 97)
        (nil)))

(insn 18 16 20 (set (reg:SI 97)
        (mem:SI (reg:SI 96) 0)) 69 {*pa.md:2099} (nil)
    (expr_list:REG_DEAD (reg:SI 96)
        (nil)))

(insn 20 18 21 (set (reg:SI 96)
        (reg:SI 97)) 69 {*pa.md:2099} (nil)
    (expr_list:REG_DEAD (reg:SI 97)
        (nil)))

For some reason not obvious to me, the reloads are not done properly for
insns 18 and 20.  In paricular, SI 97 isn't eliminated.  The rtl from the
greg pass is below.  Any thoughts on what is going wrong?

Dave
-- 
J. David Anglin                                  dave.anglin@nrc.ca
National Research Council of Canada              (613) 990-0752 (FAX: 952-6605)

;; Function main

Spilling for insn 13.
Using reg 1 for reload 0
Spilling for insn 15.
Using reg 20 for reload 1
Spilling for insn 16.
Using reg 20 for reload 0
Using reg 20 for reload 1
Spilling for insn 18.
Using reg 20 for reload 0
Using reg 20 for reload 1
Spilling for insn 20.
Using reg 20 for reload 0
Using reg 20 for reload 1
Spilling for insn 21.
Using reg 20 for reload 1
Spilling for insn 22.
Using reg 21 for reload 0

Reloads for insn # 13
Reload 0: reload_out (SI) = (reg:SI 97)
	R1_REGS, RELOAD_FOR_OUTPUT (opnum = 0)
	reload_out_reg: (reg:SI 97)
	reload_reg_rtx: (reg:SI 1 %r1)

Reloads for insn # 15
Reload 0: GENERAL_REGS, RELOAD_FOR_OUTPUT (opnum = 0)
	reload_out_reg: (reg:SI 97)
Reload 1: reload_in (SI) = (reg:SI 97)
	reload_out (SI) = (reg:SI 97)
	GENERAL_REGS, RELOAD_OTHER (opnum = 1)
	reload_in_reg: (reg:SI 97)
	reload_out_reg: (reg:SI 97)
	reload_reg_rtx: (reg:SI 20 %r20)

Reloads for insn # 16
Reload 0: reload_out (SI) = (reg:SI 96)
	GENERAL_REGS, RELOAD_FOR_OUTPUT (opnum = 0)
	reload_out_reg: (reg:SI 96)
	reload_reg_rtx: (reg:SI 21 %r21)
Reload 1: reload_in (SI) = (reg:SI 97)
	GENERAL_REGS, RELOAD_FOR_INPUT (opnum = 1)
	reload_in_reg: (reg:SI 97)
	reload_reg_rtx: (reg:SI 21 %r21)

Reloads for insn # 18
Reload 0: reload_in (SI) = (reg:SI 96)
	GENERAL_REGS, RELOAD_FOR_OPERAND_ADDRESS (opnum = 1)
	reload_in_reg: (reg:SI 96)
	reload_reg_rtx: (reg:SI 1 %r1)
Reload 1: reload_out (SI) = (reg:SI 97)
	GENERAL_REGS, RELOAD_FOR_OUTPUT (opnum = 0)
	reload_out_reg: (reg:SI 97)
	reload_reg_rtx: (reg:SI 1 %r1)

Reloads for insn # 20
Reload 0: reload_out (SI) = (reg:SI 96)
	GENERAL_REGS, RELOAD_FOR_OUTPUT (opnum = 0)
	reload_out_reg: (reg:SI 96)
	reload_reg_rtx: (reg:SI 20 %r20)
Reload 1: reload_in (SI) = (reg:SI 97)
	GENERAL_REGS, RELOAD_FOR_INPUT (opnum = 1)
	reload_in_reg: (reg:SI 97)
	reload_reg_rtx: (reg:SI 20 %r20)

Reloads for insn # 21
Reload 0: GENERAL_REGS, RELOAD_FOR_OUTPUT (opnum = 0)
	reload_out_reg: (reg:SI 96)
Reload 1: reload_in (SI) = (reg:SI 96)
	reload_out (SI) = (reg:SI 96)
	GENERAL_REGS, RELOAD_OTHER (opnum = 1)
	reload_in_reg: (reg:SI 96)
	reload_out_reg: (reg:SI 96)
	reload_reg_rtx: (reg:SI 21 %r21)

Reloads for insn # 22
Reload 0: reload_in (SI) = (reg:SI 96)
	GENERAL_REGS, RELOAD_FOR_INPUT (opnum = 1)
	reload_in_reg: (reg:SI 96)
	reload_reg_rtx: (reg:SI 1 %r1)
;; Register dispositions:
94 in 4  95 in 20  98 in 20  99 in 20  100 in 20  

;; Hard regs used:  1 2 3 4 19 20 21 28 30

(note 2 0 42 NOTE_INSN_DELETED -1347440721)

;; Start of basic block 0, registers live: 3 [%r3] 19 [%r19] 30 [%r30]
(note 42 2 5 [bb 0] NOTE_INSN_BASIC_BLOCK -1347440721)

(insn 5 42 3 (set (reg:SI 4 %r4 [94])
        (reg:SI 19 %r19)) 69 {*pa.md:2099} (nil)
    (nil))

(note 3 5 6 NOTE_INSN_FUNCTION_BEG -1347440721)

(call_insn 6 3 8 (parallel[ 
            (call (mem:SI (symbol_ref:SI ("@__main")) 0)
                (const_int 16 [0x10]))
            (clobber (reg:SI 2 %r2))
            (use (const_int 0 [0x0]))
        ] ) 270 {call_internal_symref} (nil)
    (expr_list:REG_EH_REGION (const_int 0 [0x0])
        (nil))
    (expr_list (use (reg:SI 19 %r19))
        (nil)))

(insn 8 6 13 (set (reg:SI 19 %r19)
        (reg:SI 4 %r4 [94])) 69 {*pa.md:2099} (nil)
    (nil))

(insn 13 8 46 (set (reg:SI 1 %r1)
        (plus:SI (reg:SI 19 %r19)
            (high:SI (symbol_ref/u:SI ("*L$C0000"))))) 80 {*pa.md:2326} (nil)
    (nil))

(insn 46 13 49 (set (mem:SI (plus:SI (reg/f:SI 3 %r3)
                (const_int 12 [0xc])) 0)
        (reg:SI 1 %r1)) 69 {*pa.md:2099} (nil)
    (nil))

(insn 49 46 15 (set (reg:SI 20 %r20)
        (mem:SI (plus:SI (reg/f:SI 3 %r3)
                (const_int 12 [0xc])) 0)) 69 {*pa.md:2099} (nil)
    (nil))

(insn 15 49 52 (set (reg:SI 20 %r20)
        (mem:SI (lo_sum:SI (reg:SI 20 %r20)
                (unspec:SI[ 
                        (symbol_ref/u:SI ("*L$C0000"))
                    ]  0)) 0)) 82 {*pa.md:2352} (nil)
    (nil))

(insn 52 15 58 (set (mem:SI (plus:SI (reg/f:SI 3 %r3)
                (const_int 12 [0xc])) 0)
        (reg:SI 20 %r20)) 69 {*pa.md:2099} (nil)
    (nil))

(insn 58 52 16 (set (reg:SI 21 %r21)
        (mem:SI (plus:SI (reg/f:SI 3 %r3)
                (const_int 12 [0xc])) 0)) 69 {*pa.md:2099} (nil)
    (nil))

(insn 16 58 55 (set (reg:SI 21 %r21)
        (reg:SI 21 %r21)) 69 {*pa.md:2099} (nil)
    (nil))

(insn 55 16 61 (set (mem:SI (plus:SI (reg/f:SI 3 %r3)
                (const_int 8 [0x8])) 0)
        (reg:SI 21 %r21)) 69 {*pa.md:2099} (nil)
    (nil))

(insn 61 55 18 (set (reg:SI 1 %r1)
        (mem:SI (plus:SI (reg/f:SI 3 %r3)
                (const_int 8 [0x8])) 0)) 69 {*pa.md:2099} (nil)
    (nil))

(insn 18 61 64 (set (reg:SI 1 %r1)
        (mem:SI (reg:SI 1 %r1) 0)) 69 {*pa.md:2099} (nil)
    (nil))

(insn 64 18 70 (set (reg:SI 97)
        (reg:SI 1 %r1)) 69 {*pa.md:2099} (nil)
    (nil))

(insn 70 64 20 (set (reg:SI 20 %r20)
        (reg:SI 97)) 69 {*pa.md:2099} (nil)
    (nil))

(insn 20 70 67 (set (reg:SI 20 %r20)
        (reg:SI 20 %r20)) 69 {*pa.md:2099} (nil)
    (nil))

(insn 67 20 73 (set (mem:SI (plus:SI (reg/f:SI 3 %r3)
                (const_int 8 [0x8])) 0)
        (reg:SI 20 %r20)) 69 {*pa.md:2099} (nil)
    (nil))

(insn 73 67 21 (set (reg:SI 21 %r21)
        (mem:SI (plus:SI (reg/f:SI 3 %r3)
                (const_int 8 [0x8])) 0)) 69 {*pa.md:2099} (nil)
    (nil))

(insn 21 73 76 (set (reg:SI 21 %r21)
        (plus:SI (reg:SI 21 %r21)
            (const_int 7 [0x7]))) 169 {addsi3} (nil)
    (nil))

(insn 76 21 79 (set (mem:SI (plus:SI (reg/f:SI 3 %r3)
                (const_int 8 [0x8])) 0)
        (reg:SI 21 %r21)) 69 {*pa.md:2099} (nil)
    (nil))

(insn 79 76 22 (set (reg:SI 1 %r1)
        (mem:SI (plus:SI (reg/f:SI 3 %r3)
                (const_int 8 [0x8])) 0)) 69 {*pa.md:2099} (nil)
    (nil))

(insn 22 79 23 (set (reg:SI 20 %r20 [95])
        (plus:SI (reg:SI 1 %r1)
            (const_int 7 [0x7]))) 169 {addsi3} (nil)
    (nil))

(insn 23 22 25 (set (reg:SI 20 %r20 [98])
        (lshiftrt:SI (reg:SI 20 %r20 [95])
            (const_int 3 [0x3]))) 256 {lshrsi3} (nil)
    (expr_list:REG_EQUAL (udiv:SI (reg:SI 20 %r20 [95])
            (const_int 8 [0x8]))
        (nil)))

(insn 25 23 27 (set (reg:SI 20 %r20 [99])
        (reg:SI 20 %r20 [98])) 69 {*pa.md:2099} (nil)
    (nil))

(insn 27 25 30 (set (reg:SI 20 %r20 [100])
        (ashift:SI (reg:SI 20 %r20 [99])
            (const_int 3 [0x3]))) 242 {*pa.md:5111} (nil)
    (expr_list:REG_EQUAL (mult:SI (reg:SI 20 %r20 [98])
            (const_int 8 [0x8]))
        (nil)))

(insn 30 27 37 (set (reg/f:SI 30 %r30)
        (plus:SI (reg/f:SI 30 %r30)
            (reg:SI 20 %r20 [100]))) 169 {addsi3} (nil)
    (nil))

(note 37 30 39 NOTE_INSN_FUNCTION_END -1347440721)

(insn 39 37 41 (clobber (reg/i:SI 28 %r28)) -1 (nil)
    (nil))

(insn 41 39 43 (use (reg/i:SI 28 %r28)) -1 (nil)
    (nil))
;; End of basic block 0, registers live:
 3 [%r3] 19 [%r19] 28 [%r28] 30 [%r30]

(note 43 41 0 NOTE_INSN_DELETED -1347440721)


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