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Patches for HP-UX support on IA64
- To: gcc-patches at gcc dot gnu dot org
- Subject: Patches for HP-UX support on IA64
- From: Steve Ellcey <sje at cup dot hp dot com>
- Date: Tue, 9 Jan 2001 15:48:29 -0800 (PST)
- Reply-To: sje at cup dot hp dot com
I have a set of changes I would like to have reviewed and checked in to
support HP-UX on the IA64 platform including support for an ILP32 mode.
Most of the changes are specific to hp-ux (New files: hpux.h,
hpux_longdouble.h, quadlib.c, t-hpux in config/ia64) or at least to IA64
(Changes to ia64.c, ia64.h, ia64.md in config/ia64) but I did make
changes to optabs.c, simplify-rtx.c, and combine.c because when
converting a 32 bit pointer to a 64 bit address on IA64 the IA64 does
not use a signed or unsigned extension but rather a special instruction
called 'addp4' which zeros out the high bits but then copies bits 30&31
into bits 61&62. My solution was to create a special instruction in
ia64.md called extend_ptr and then, if this instruction exists, use it
instead of a signed or unsigned shift to do a pointer extension. The
changes to optabs.c, simplify-rtx.c, and combine.c check for
HAVE_extend_ptr and then take the proper action if it is defined.
Here is a ChangeLog entry followed by all the diffs, please let me know
if you have any questions or if you can review and check in these
changes, I do have a copyright assignment on file.
2001-01-09 Steve Ellcey <sje@cup.hp.com>
* config.gcc (ia64*-*-hpux*): New case.
* optabs.c (can_extend_p): Check for HAVE_extend_ptr.
* simplify-rtx.c (simplify_unary_operation): Likewise.
* combine.c (nonzero_bits): Likewise.
(num_sign_bit_copies): Likewise.
* config/ia64/ia64.c (ia64_function_arg): Add use of TARGET_80LD
(ia64_function_value): Likewise.
(ia64_asm_output_external): Move ASM_GLOBALIZE_LABEL after declaration.
(rtx_needs_barrier): Add unspec 24 (extend_ptr) to instructions.
* config/ia64/ia64.h (MASK_ILP32): New macro for ILP32 support
(TARGET_ILP32): Likewise.
(SUBTARGET_SWITCHES): Add SUBTARGET_SWITCHES support.
(POINTER_SIZE, LONG_TYPE_SIZE) Modify for ILP32 support.
(ASM_OUTPUT_DOUBLE) Add WORDS_BIG_ENDIAN support.
(ASM_OUTPUT_INT) Add ILP32 support.
(ASM_OUTPUT_XDATA_INT) Likewise.
* config/ia64/ia64.md: Add TARGET_80LD and TARGET_HPUX usage,
Add extend_ptr instruction, Add floatdidf2 and floatdisf2 for
use when TARGET_80LD is not defined.
* config/ia64/hpux.h: New file for HP-UX support.
* config/ia64/hpux_longdouble.h: New file for 128 bit floating point
support on HP-UX, copied, then modified from config/pa/long_double.h.
* config/ia64/quadlib.c: New file for 128 bit floating point support
on HP-UX, copied, then modified from config/pa/quadlib.c.
* config/ia64/t-hpux: New file for HP-UX support.
*** config.gcc@@/main/LATEST Sun Dec 3 12:47:15 2000
--- config.gcc Tue Dec 12 10:40:45 2000
*************** ia64*-*-linux*)
*** 1537,1542 ****
--- 1537,1557 ----
fi
float_format=i386
;;
+ ia64*-*-hpux*)
+ tm_file=ia64/hpux.h
+ tmake_file="t-hpux ia64/t-ia64 ia64/t-glibc"
+ if test x$gas = xyes; then
+ target_cpu_default="${target_cpu_default}|MASK_GNU_AS"
+ fi
+ if test x$gnu_ld = xyes; then
+ target_cpu_default="${target_cpu_default}|MASK_GNU_LD"
+ fi
+ target_cpu_default="MASK_GNU_AS|MASK_GNU_LD"
+ if test x$enable_threads = xyes; then
+ thread_file='posix'
+ fi
+ float_format=i386
+ ;;
m32r-*-elf*)
extra_parts="crtinit.o crtfini.o"
;;
*** optabs.c@@/main/LATEST Sun Dec 3 12:48:25 2000
--- optabs.c Tue Jan 9 14:32:10 2001
*************** can_extend_p (to_mode, from_mode, unsign
*** 3867,3873 ****
enum machine_mode to_mode, from_mode;
int unsignedp;
{
! return extendtab[(int) to_mode][(int) from_mode][unsignedp != 0];
}
/* Generate the body of an insn to extend Y (with mode MFROM)
--- 3867,3877 ----
enum machine_mode to_mode, from_mode;
int unsignedp;
{
! #ifdef HAVE_extend_ptr
! return CODE_FOR_extend_ptr;
! #else
! return extendtab[(int) to_mode][(int) from_mode][unsignedp != 0];
! #endif
}
/* Generate the body of an insn to extend Y (with mode MFROM)
*** simplify-rtx.c@@/main/LATEST Tue Jan 9 13:32:03 2001
--- simplify-rtx.c Tue Jan 9 14:34:25 2001
*************** simplify_unary_operation (code, mode, op
*** 620,626 ****
&& GET_CODE (XEXP (XEXP (op, 0), 1)) == LABEL_REF)
return XEXP (op, 0);
! #ifdef POINTERS_EXTEND_UNSIGNED
if (! POINTERS_EXTEND_UNSIGNED
&& mode == Pmode && GET_MODE (op) == ptr_mode
&& CONSTANT_P (op))
--- 620,626 ----
&& GET_CODE (XEXP (XEXP (op, 0), 1)) == LABEL_REF)
return XEXP (op, 0);
! #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_extend_ptr)
if (! POINTERS_EXTEND_UNSIGNED
&& mode == Pmode && GET_MODE (op) == ptr_mode
&& CONSTANT_P (op))
*************** simplify_unary_operation (code, mode, op
*** 628,634 ****
#endif
break;
! #ifdef POINTERS_EXTEND_UNSIGNED
case ZERO_EXTEND:
if (POINTERS_EXTEND_UNSIGNED
&& mode == Pmode && GET_MODE (op) == ptr_mode
--- 628,634 ----
#endif
break;
! #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_extend_ptr)
case ZERO_EXTEND:
if (POINTERS_EXTEND_UNSIGNED
&& mode == Pmode && GET_MODE (op) == ptr_mode
*** combine.c@@/main/LATEST Tue Jan 9 13:31:50 2001
--- combine.c Tue Jan 9 14:35:26 2001
*************** nonzero_bits (x, mode)
*** 8015,8021 ****
switch (code)
{
case REG:
! #ifdef POINTERS_EXTEND_UNSIGNED
/* If pointers extend unsigned and this is a pointer in Pmode, say that
all the bits above ptr_mode are known to be zero. */
if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
--- 8015,8021 ----
switch (code)
{
case REG:
! #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_extend_ptr)
/* If pointers extend unsigned and this is a pointer in Pmode, say that
all the bits above ptr_mode are known to be zero. */
if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
*************** num_sign_bit_copies (x, mode)
*** 8455,8461 ****
{
case REG:
! #ifdef POINTERS_EXTEND_UNSIGNED
/* If pointers extend signed and this is a pointer in Pmode, say that
all the bits above ptr_mode are known to be sign bit copies. */
if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
--- 8455,8461 ----
{
case REG:
! #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_extend_ptr)
/* If pointers extend signed and this is a pointer in Pmode, say that
all the bits above ptr_mode are known to be sign bit copies. */
if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
*** config/ia64/ia64.c@@/main/LATEST Tue Jan 9 12:29:01 2001
--- config/ia64/ia64.c Tue Jan 9 14:50:20 2001
*************** ia64_function_arg (cum, mode, type, name
*** 2833,2839 ****
/* Integral and aggregates go in general registers. If we have run out of
FR registers, then FP values must also go in general registers. This can
happen when we have a SFmode HFA. */
! else if (! FLOAT_MODE_P (mode) || cum->fp_regs == MAX_ARGUMENT_SLOTS)
return gen_rtx_REG (mode, basereg + cum->words + offset);
/* If there is a prototype, then FP values go in a FR register when
--- 2833,2840 ----
/* Integral and aggregates go in general registers. If we have run out of
FR registers, then FP values must also go in general registers. This can
happen when we have a SFmode HFA. */
! else if (((mode == TFmode) && (!TARGET_80LD)) ||
! (! FLOAT_MODE_P (mode) || cum->fp_regs == MAX_ARGUMENT_SLOTS))
return gen_rtx_REG (mode, basereg + cum->words + offset);
/* If there is a prototype, then FP values go in a FR register when
*************** ia64_function_value (valtype, func)
*** 3113,3119 ****
else
return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
}
! else if (FLOAT_TYPE_P (valtype))
return gen_rtx_REG (mode, FR_ARG_FIRST);
else
return gen_rtx_REG (mode, GR_RET_FIRST);
--- 3114,3121 ----
else
return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
}
! else if (((mode != TFmode) || (TARGET_80LD)) &&
! (FLOAT_TYPE_P (valtype)))
return gen_rtx_REG (mode, FR_ARG_FIRST);
else
return gen_rtx_REG (mode, GR_RET_FIRST);
*************** ia64_asm_output_external (file, decl, na
*** 3562,3567 ****
--- 3564,3570 ----
/* assemble_name will set TREE_SYMBOL_REFERENCED, so we must save and
restore it. */
+ ASM_GLOBALIZE_LABEL (file, name);
save_referenced = TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl));
if (TREE_CODE (decl) == FUNCTION_DECL)
{
*************** ia64_asm_output_external (file, decl, na
*** 3571,3577 ****
fprintf (file, TYPE_OPERAND_FMT, "function");
putc ('\n', file);
}
- ASM_GLOBALIZE_LABEL (file, name);
TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)) = save_referenced;
}
--- 3574,3579 ----
*************** rtx_needs_barrier (x, flags, pred)
*** 4249,4254 ****
--- 4251,4259 ----
case 22: /* bundle selector */
case 23: /* cycle display */
break;
+ case 24: /* extend_ptr (addp4) */
+ need_barrier = 1;
+ break;
case 5: /* recip_approx */
need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
*** config/ia64/ia64.h@@/main/LATEST Tue Jan 9 12:22:53 2001
--- config/ia64/ia64.h Tue Jan 9 14:52:42 2001
*************** extern int target_flags;
*** 71,76 ****
--- 71,78 ----
#define MASK_DWARF2_ASM 0x40000000 /* test dwarf2 line info via gas. */
+ #define MASK_ILP32 0x20000000 /* Generate ILP32 code. */
+
#define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
#define TARGET_GNU_AS (target_flags & MASK_GNU_AS)
*************** extern int target_flags;
*** 102,107 ****
--- 104,111 ----
#define TARGET_DWARF2_ASM (target_flags & MASK_DWARF2_ASM)
+ #define TARGET_ILP32 (target_flags & MASK_ILP32)
+
/* This macro defines names of command options to set and clear bits in
`target_flags'. Its definition is an initializer with a subgrouping for
each command option. */
*************** extern int target_flags;
*** 148,153 ****
--- 152,158 ----
N_("Enable Dwarf 2 line debug info via GNU as")}, \
{ "no-dwarf2-asm", -MASK_DWARF2_ASM, \
N_("Disable Dwarf 2 line debug info via GNU as")}, \
+ SUBTARGET_SWITCHES \
{ "", TARGET_DEFAULT | TARGET_CPU_DEFAULT, \
NULL } \
}
*************** extern int target_flags;
*** 162,167 ****
--- 167,178 ----
#define TARGET_CPU_DEFAULT 0
#endif
+ /* Define if there is no overriding one in target specific files. */
+
+ #ifndef SUBTARGET_SWITCHES
+ #define SUBTARGET_SWITCHES
+ #endif
+
/* This macro is similar to `TARGET_SWITCHES' but defines names of command
options that have values. Its definition is an initializer with a
subgrouping for each command option. */
*************** extern const char *ia64_fixed_range_stri
*** 214,220 ****
This should be defined if `SIZE_TYPE' depends on target dependent flags
which are not accessible to the preprocessor. Otherwise, it should not be
defined. */
! /* ??? Needs to be defined for P64 code. */
/* #define NO_BUILTIN_SIZE_TYPE */
/* If this macro is defined, the preprocessor will not define the builtin macro
--- 225,233 ----
This should be defined if `SIZE_TYPE' depends on target dependent flags
which are not accessible to the preprocessor. Otherwise, it should not be
defined. */
!
! /* This is always "long" so it doesn't "change" in ILP32 vs. LP64 */
!
/* #define NO_BUILTIN_SIZE_TYPE */
/* If this macro is defined, the preprocessor will not define the builtin macro
*************** extern const char *ia64_fixed_range_stri
*** 224,230 ****
This should be defined if `PTRDIFF_TYPE' depends on target dependent flags
which are not accessible to the preprocessor. Otherwise, it should not be
defined. */
! /* ??? Needs to be defined for P64 code. */
/* #define NO_BUILTIN_PTRDIFF_TYPE */
/* A C string constant that tells the GNU CC driver program options to pass to
--- 237,245 ----
This should be defined if `PTRDIFF_TYPE' depends on target dependent flags
which are not accessible to the preprocessor. Otherwise, it should not be
defined. */
!
! /* This is always "long" so it doesn't "change" in ILP32 vs. LP64 */
!
/* #define NO_BUILTIN_PTRDIFF_TYPE */
/* A C string constant that tells the GNU CC driver program options to pass to
*************** extern const char *ia64_fixed_range_stri
*** 309,324 ****
/* Width of a pointer, in bits. You must specify a value no wider than the
width of `Pmode'. If it is not equal to the width of `Pmode', you must
define `POINTERS_EXTEND_UNSIGNED'. */
- /* ??? Implement optional 32 bit pointer size later? */
- #define POINTER_SIZE 64
! /* A C expression whose value is nonzero if pointers that need to be extended
! from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and zero if
! they are zero-extended.
You need not define this macro if the `POINTER_SIZE' is equal to the width
! of `Pmode'. */
! /* ??? May need this for 32 bit pointers. */
/* #define POINTERS_EXTEND_UNSIGNED */
/* A macro to update MODE and UNSIGNEDP when an object whose type is TYPE and
--- 324,343 ----
/* Width of a pointer, in bits. You must specify a value no wider than the
width of `Pmode'. If it is not equal to the width of `Pmode', you must
define `POINTERS_EXTEND_UNSIGNED'. */
! #define POINTER_SIZE (TARGET_ILP32 ? 32 : 64)
!
! /* A C expression whose value is zero if pointers that need to be extended
! from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and
! nonzero if they are zero-extended.
You need not define this macro if the `POINTER_SIZE' is equal to the width
! of `Pmode'.
!
! If there is a extend_ptr instruction (HAVE_extend_ptr is defined) then
! it doesn't matter what POINTERS_EXTEND_UNSIGNED is set to as long as
! it is defined. */
!
/* #define POINTERS_EXTEND_UNSIGNED */
/* A macro to update MODE and UNSIGNEDP when an object whose type is TYPE and
*************** while (0)
*** 439,453 ****
/* A C expression for the size in bits of the type `long' on the target
machine. If you don't define this, the default is one word. */
! /* ??? Should be 32 for ILP32 code. */
! #define LONG_TYPE_SIZE 64
/* Maximum number for the size in bits of the type `long' on the target
machine. If this is undefined, the default is `LONG_TYPE_SIZE'. Otherwise,
it is the constant value that is the largest value that `LONG_TYPE_SIZE' can
have at run-time. This is used in `cpp'. */
! /* ??? Should be 64 for ILP32 code. */
! /* #define MAX_LONG_TYPE_SIZE */
/* A C expression for the size in bits of the type `long long' on the target
machine. If you don't define this, the default is two words. If you want
--- 458,472 ----
/* A C expression for the size in bits of the type `long' on the target
machine. If you don't define this, the default is one word. */
!
! #define LONG_TYPE_SIZE (TARGET_ILP32 ? 32 : 64)
/* Maximum number for the size in bits of the type `long' on the target
machine. If this is undefined, the default is `LONG_TYPE_SIZE'. Otherwise,
it is the constant value that is the largest value that `LONG_TYPE_SIZE' can
have at run-time. This is used in `cpp'. */
!
! #define MAX_LONG_TYPE_SIZE 64
/* A C expression for the size in bits of the type `long long' on the target
machine. If you don't define this, the default is two words. If you want
*************** do { \
*** 2038,2044 ****
long t[2]; \
REAL_VALUE_TO_TARGET_DOUBLE (VALUE, t); \
fprintf (FILE, "\tdata8 0x%08lx%08lx\n", \
! t[1] & 0xffffffff, t[0] & 0xffffffff); \
} while (0)
#define ASM_OUTPUT_FLOAT(FILE,VALUE) \
--- 2057,2064 ----
long t[2]; \
REAL_VALUE_TO_TARGET_DOUBLE (VALUE, t); \
fprintf (FILE, "\tdata8 0x%08lx%08lx\n", \
! (WORDS_BIG_ENDIAN ? t[0] : t[1]) & 0xffffffff, \
! (WORDS_BIG_ENDIAN ? t[1] : t[0]) & 0xffffffff); \
} while (0)
#define ASM_OUTPUT_FLOAT(FILE,VALUE) \
*************** do { \
*** 2073,2084 ****
/* This is how to output an assembler line defining an `int' constant.
We also handle symbol output here. */
- /* ??? For ILP32, also need to handle function addresses here. */
-
#define ASM_OUTPUT_INT(FILE, VALUE) \
do { \
fprintf (FILE, "\tdata4\t"); \
output_addr_const (FILE, (VALUE)); \
fprintf (FILE, "\n"); \
} while (0)
--- 2093,2106 ----
/* This is how to output an assembler line defining an `int' constant.
We also handle symbol output here. */
#define ASM_OUTPUT_INT(FILE, VALUE) \
do { \
fprintf (FILE, "\tdata4\t"); \
+ if (!(TARGET_NO_PIC || TARGET_AUTO_PIC) && SYMBOL_REF_FLAG (VALUE)) \
+ fprintf (FILE, "@fptr("); \
output_addr_const (FILE, (VALUE)); \
+ if (!(TARGET_NO_PIC || TARGET_AUTO_PIC) && SYMBOL_REF_FLAG (VALUE)) \
+ fprintf (FILE, ")"); \
fprintf (FILE, "\n"); \
} while (0)
*************** do { \
*** 2119,2130 ****
/* This is how to output an assembler line defining an `int' constant
to an xdata segment. We also handle symbol output here. */
- /* ??? For ILP32, also need to handle function addresses here. */
-
#define ASM_OUTPUT_XDATA_INT(FILE, SECTION, VALUE) \
do { \
fprintf (FILE, "\t.xdata4\t\"%s\", ", SECTION); \
output_addr_const (FILE, (VALUE)); \
fprintf (FILE, "\n"); \
} while (0)
--- 2141,2158 ----
/* This is how to output an assembler line defining an `int' constant
to an xdata segment. We also handle symbol output here. */
#define ASM_OUTPUT_XDATA_INT(FILE, SECTION, VALUE) \
do { \
+ int need_closing_paren = 0; \
fprintf (FILE, "\t.xdata4\t\"%s\", ", SECTION); \
+ if (!(TARGET_NO_PIC || TARGET_AUTO_PIC) && GET_CODE (VALUE) == SYMBOL_REF) \
+ { \
+ fprintf (FILE, SYMBOL_REF_FLAG (VALUE) ? "@fptr(" : "@segrel("); \
+ need_closing_paren = 1; \
+ } \
output_addr_const (FILE, (VALUE)); \
+ if (need_closing_paren) \
+ fprintf (FILE, ")"); \
fprintf (FILE, "\n"); \
} while (0)
*************** enum fetchop_code {
*** 2927,2931 ****
--- 2955,2968 ----
#define MD_EXPAND_BUILTIN(EXP, TARGET, SUBTARGET, MODE, IGNORE) \
ia64_expand_builtin ((EXP), (TARGET), (SUBTARGET), (MODE), (IGNORE))
+
+ #ifndef TARGET_HPUX
+ #define TARGET_HPUX 0
+ #endif
+ #ifdef INTEL_EXTENDED_IEEE_FORMAT
+ #define TARGET_80LD 1
+ #else
+ #define TARGET_80LD 0
+ #endif
/* End of ia64.h */
*** config/ia64/ia64.md@@/main/LATEST Tue Jan 9 12:26:46 2001
--- config/ia64/ia64.md Tue Jan 9 14:49:16 2001
***************
*** 947,953 ****
(define_expand "movtf"
[(set (match_operand:TF 0 "general_operand" "")
(match_operand:TF 1 "general_operand" ""))]
! ""
"
{
/* We must support TFmode loads into general registers for stdarg/vararg
--- 947,953 ----
(define_expand "movtf"
[(set (match_operand:TF 0 "general_operand" "")
(match_operand:TF 1 "general_operand" ""))]
! "TARGET_80LD"
"
{
/* We must support TFmode loads into general registers for stdarg/vararg
***************
*** 1024,1030 ****
(const_int 0)])
(set (match_operand:TF 0 "register_operand" "=f")
(match_operand:TF 1 "nonmemory_operand" "fG")))]
! "TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
"(%J2) mov %0 = %F1"
[(set_attr "itanium_class" "fmisc")
(set_attr "predicable" "no")])
--- 1024,1030 ----
(const_int 0)])
(set (match_operand:TF 0 "register_operand" "=f")
(match_operand:TF 1 "nonmemory_operand" "fG")))]
! "TARGET_80LD && TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
"(%J2) mov %0 = %F1"
[(set_attr "itanium_class" "fmisc")
(set_attr "predicable" "no")])
***************
*** 1032,1038 ****
(define_insn "*movtf_internal_astep"
[(set (match_operand:TF 0 "destination_tfmode_operand" "=f,f, m")
(match_operand:TF 1 "general_tfmode_operand" "fG,m,fG"))]
! "TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
"@
mov %0 = %F1
ldfe %0 = %1%P1
--- 1032,1038 ----
(define_insn "*movtf_internal_astep"
[(set (match_operand:TF 0 "destination_tfmode_operand" "=f,f, m")
(match_operand:TF 1 "general_tfmode_operand" "fG,m,fG"))]
! "TARGET_80LD && TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
"@
mov %0 = %F1
ldfe %0 = %1%P1
***************
*** 1043,1049 ****
(define_insn "*movtf_internal"
[(set (match_operand:TF 0 "destination_tfmode_operand" "=f,f, m")
(match_operand:TF 1 "general_tfmode_operand" "fG,m,fG"))]
! "! TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
"@
mov %0 = %F1
ldfe %0 = %1%P1
--- 1043,1049 ----
(define_insn "*movtf_internal"
[(set (match_operand:TF 0 "destination_tfmode_operand" "=f,f, m")
(match_operand:TF 1 "general_tfmode_operand" "fG,m,fG"))]
! "TARGET_80LD && ! TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
"@
mov %0 = %F1
ldfe %0 = %1%P1
***************
*** 1147,1153 ****
[(set (match_operand:TF 0 "fr_nonimmediate_operand" "=f,f,f,f,Q")
(float_extend:TF
(match_operand:SF 1 "grfr_nonimmediate_operand" "0,f,Q,*r,f")))]
! ""
"@
mov %0 = %1
mov %0 = %1
--- 1147,1153 ----
[(set (match_operand:TF 0 "fr_nonimmediate_operand" "=f,f,f,f,Q")
(float_extend:TF
(match_operand:SF 1 "grfr_nonimmediate_operand" "0,f,Q,*r,f")))]
! "TARGET_80LD"
"@
mov %0 = %1
mov %0 = %1
***************
*** 1170,1176 ****
[(set (match_operand:TF 0 "fr_nonimmediate_operand" "=f,f,f,f,Q")
(float_extend:TF
(match_operand:DF 1 "grfr_nonimmediate_operand" "0,f,Q,*r,f")))]
! ""
"@
mov %0 = %1
mov %0 = %1
--- 1170,1176 ----
[(set (match_operand:TF 0 "fr_nonimmediate_operand" "=f,f,f,f,Q")
(float_extend:TF
(match_operand:DF 1 "grfr_nonimmediate_operand" "0,f,Q,*r,f")))]
! "TARGET_80LD"
"@
mov %0 = %1
mov %0 = %1
***************
*** 1199,1212 ****
(define_insn "trunctfsf2"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(float_truncate:SF (match_operand:TF 1 "fr_register_operand" "f")))]
! ""
"fnorm.s %0 = %1%B0"
[(set_attr "itanium_class" "fmac")])
(define_insn "trunctfdf2"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
(float_truncate:DF (match_operand:TF 1 "fr_register_operand" "f")))]
! ""
"fnorm.d %0 = %1%B0"
[(set_attr "itanium_class" "fmac")])
--- 1199,1212 ----
(define_insn "trunctfsf2"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(float_truncate:SF (match_operand:TF 1 "fr_register_operand" "f")))]
! "TARGET_80LD"
"fnorm.s %0 = %1%B0"
[(set_attr "itanium_class" "fmac")])
(define_insn "trunctfdf2"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
(float_truncate:DF (match_operand:TF 1 "fr_register_operand" "f")))]
! "TARGET_80LD"
"fnorm.d %0 = %1%B0"
[(set_attr "itanium_class" "fmac")])
***************
*** 1215,1224 ****
(define_insn "floatditf2"
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(float:TF (match_operand:DI 1 "fr_register_operand" "f")))]
! ""
"fcvt.xf %0 = %1"
[(set_attr "itanium_class" "fcvtfx")])
(define_insn "fix_truncsfdi2"
[(set (match_operand:DI 0 "fr_register_operand" "=f")
(fix:DI (match_operand:SF 1 "fr_register_operand" "f")))]
--- 1215,1238 ----
(define_insn "floatditf2"
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(float:TF (match_operand:DI 1 "fr_register_operand" "f")))]
! "TARGET_80LD"
"fcvt.xf %0 = %1"
[(set_attr "itanium_class" "fcvtfx")])
+ (define_insn "floatdidf2"
+ [(set (match_operand:DF 0 "register_operand" "=f")
+ (float:DF (match_operand:DI 1 "register_operand" "f")))]
+ "!TARGET_80LD"
+ "fcvt.xf %0 = %1\;;;\;fnorm.d %0 = %0%B0"
+ [(set_attr "type" "unknown")])
+
+ (define_insn "floatdisf2"
+ [(set (match_operand:SF 0 "register_operand" "=f")
+ (float:SF (match_operand:DI 1 "register_operand" "f")))]
+ "!TARGET_80LD"
+ "fcvt.xf %0 = %1\;;;\;fnorm.s %0 = %0%B0"
+ [(set_attr "type" "unknown")])
+
(define_insn "fix_truncsfdi2"
[(set (match_operand:DI 0 "fr_register_operand" "=f")
(fix:DI (match_operand:SF 1 "fr_register_operand" "f")))]
***************
*** 1236,1242 ****
(define_insn "fix_trunctfdi2"
[(set (match_operand:DI 0 "fr_register_operand" "=f")
(fix:DI (match_operand:TF 1 "fr_register_operand" "f")))]
! ""
"fcvt.fx.trunc %0 = %1%B0"
[(set_attr "itanium_class" "fcvtfx")])
--- 1250,1256 ----
(define_insn "fix_trunctfdi2"
[(set (match_operand:DI 0 "fr_register_operand" "=f")
(fix:DI (match_operand:TF 1 "fr_register_operand" "f")))]
! "TARGET_80LD"
"fcvt.fx.trunc %0 = %1%B0"
[(set_attr "itanium_class" "fcvtfx")])
***************
*** 1244,1250 ****
[(set (match_operand:DI 0 "fr_register_operand" "=f")
(fix:DI (match_operand:TF 1 "fr_register_operand" "f")))
(use (match_operand:SI 2 "const_int_operand" ""))]
! ""
"fcvt.fx.trunc.s%2 %0 = %1%B0"
[(set_attr "itanium_class" "fcvtfx")])
--- 1258,1264 ----
[(set (match_operand:DI 0 "fr_register_operand" "=f")
(fix:DI (match_operand:TF 1 "fr_register_operand" "f")))
(use (match_operand:SI 2 "const_int_operand" ""))]
! "TARGET_80LD"
"fcvt.fx.trunc.s%2 %0 = %1%B0"
[(set_attr "itanium_class" "fcvtfx")])
***************
*** 1267,1273 ****
(define_insn "floatunsditf2"
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(unsigned_float:TF (match_operand:DI 1 "fr_register_operand" "f")))]
! ""
"fcvt.xuf %0 = %1%B0"
[(set_attr "itanium_class" "fcvtfx")])
--- 1281,1287 ----
(define_insn "floatunsditf2"
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(unsigned_float:TF (match_operand:DI 1 "fr_register_operand" "f")))]
! "TARGET_80LD"
"fcvt.xuf %0 = %1%B0"
[(set_attr "itanium_class" "fcvtfx")])
***************
*** 1288,1294 ****
(define_insn "fixuns_trunctfdi2"
[(set (match_operand:DI 0 "fr_register_operand" "=f")
(unsigned_fix:DI (match_operand:TF 1 "fr_register_operand" "f")))]
! ""
"fcvt.fxu.trunc %0 = %1%B0"
[(set_attr "itanium_class" "fcvtfx")])
--- 1302,1308 ----
(define_insn "fixuns_trunctfdi2"
[(set (match_operand:DI 0 "fr_register_operand" "=f")
(unsigned_fix:DI (match_operand:TF 1 "fr_register_operand" "f")))]
! "TARGET_80LD"
"fcvt.fxu.trunc %0 = %1%B0"
[(set_attr "itanium_class" "fcvtfx")])
***************
*** 1296,1302 ****
[(set (match_operand:DI 0 "fr_register_operand" "=f")
(unsigned_fix:DI (match_operand:TF 1 "fr_register_operand" "f")))
(use (match_operand:SI 2 "const_int_operand" ""))]
! ""
"fcvt.fxu.trunc.s%2 %0 = %1%B0"
[(set_attr "itanium_class" "fcvtfx")])
--- 1310,1316 ----
[(set (match_operand:DI 0 "fr_register_operand" "=f")
(unsigned_fix:DI (match_operand:TF 1 "fr_register_operand" "f")))
(use (match_operand:SI 2 "const_int_operand" ""))]
! "TARGET_80LD"
"fcvt.fxu.trunc.s%2 %0 = %1%B0"
[(set_attr "itanium_class" "fcvtfx")])
***************
*** 1311,1317 ****
(sign_extract:DI (match_operand:DI 1 "gr_register_operand" "r")
(match_operand:DI 2 "const_int_operand" "n")
(match_operand:DI 3 "const_int_operand" "n")))]
! ""
"extr %0 = %1, %3, %2"
[(set_attr "itanium_class" "ishf")])
--- 1325,1331 ----
(sign_extract:DI (match_operand:DI 1 "gr_register_operand" "r")
(match_operand:DI 2 "const_int_operand" "n")
(match_operand:DI 3 "const_int_operand" "n")))]
! "! TARGET_HPUX"
"extr %0 = %1, %3, %2"
[(set_attr "itanium_class" "ishf")])
***************
*** 1320,1326 ****
(zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r")
(match_operand:DI 2 "const_int_operand" "n")
(match_operand:DI 3 "const_int_operand" "n")))]
! ""
"extr.u %0 = %1, %3, %2"
[(set_attr "itanium_class" "ishf")])
--- 1334,1340 ----
(zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r")
(match_operand:DI 2 "const_int_operand" "n")
(match_operand:DI 3 "const_int_operand" "n")))]
! "! TARGET_HPUX"
"extr.u %0 = %1, %3, %2"
[(set_attr "itanium_class" "ishf")])
***************
*** 1338,1344 ****
(match_operand:DI 1 "const_int_operand" "")
(match_operand:DI 2 "const_int_operand" ""))
(match_operand:DI 3 "nonmemory_operand" ""))]
! ""
"
{
int width = INTVAL (operands[1]);
--- 1352,1358 ----
(match_operand:DI 1 "const_int_operand" "")
(match_operand:DI 2 "const_int_operand" ""))
(match_operand:DI 3 "nonmemory_operand" ""))]
! "! TARGET_HPUX"
"
{
int width = INTVAL (operands[1]);
***************
*** 2179,2185 ****
[(set (match_operand:SI 0 "register_operand" "")
(div:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")))]
! "TARGET_INLINE_DIV"
"
{
rtx op1_tf, op2_tf, op0_tf, op0_di, twon34;
--- 2193,2199 ----
[(set (match_operand:SI 0 "register_operand" "")
(div:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")))]
! "TARGET_80LD && TARGET_INLINE_DIV"
"
{
rtx op1_tf, op2_tf, op0_tf, op0_di, twon34;
***************
*** 2218,2224 ****
[(set (match_operand:SI 0 "register_operand" "")
(mod:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")))]
! "TARGET_INLINE_DIV"
"
{
rtx op2_neg, op1_di, div;
--- 2232,2238 ----
[(set (match_operand:SI 0 "register_operand" "")
(mod:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")))]
! "TARGET_80LD && TARGET_INLINE_DIV"
"
{
rtx op2_neg, op1_di, div;
***************
*** 2242,2248 ****
[(set (match_operand:SI 0 "register_operand" "")
(udiv:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")))]
! "TARGET_INLINE_DIV"
"
{
rtx op1_tf, op2_tf, op0_tf, op0_di, twon34;
--- 2256,2262 ----
[(set (match_operand:SI 0 "register_operand" "")
(udiv:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")))]
! "TARGET_80LD && TARGET_INLINE_DIV"
"
{
rtx op1_tf, op2_tf, op0_tf, op0_di, twon34;
***************
*** 2281,2287 ****
[(set (match_operand:SI 0 "register_operand" "")
(umod:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")))]
! "TARGET_INLINE_DIV"
"
{
rtx op2_neg, op1_di, div;
--- 2295,2301 ----
[(set (match_operand:SI 0 "register_operand" "")
(umod:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")))]
! "TARGET_80LD && TARGET_INLINE_DIV"
"
{
rtx op2_neg, op1_di, div;
***************
*** 2309,2315 ****
(clobber (match_scratch:TF 5 "=&f"))
(clobber (match_scratch:BI 6 "=c"))
(use (match_operand:TF 3 "fr_register_operand" "f"))]
! "TARGET_INLINE_DIV"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
--- 2323,2329 ----
(clobber (match_scratch:TF 5 "=&f"))
(clobber (match_scratch:BI 6 "=c"))
(use (match_operand:TF 3 "fr_register_operand" "f"))]
! "TARGET_80LD && TARGET_INLINE_DIV"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
***************
*** 2593,2599 ****
[(set (match_operand:DI 0 "register_operand" "")
(div:DI (match_operand:DI 1 "general_operand" "")
(match_operand:DI 2 "general_operand" "")))]
! "TARGET_INLINE_DIV"
"
{
rtx op1_tf, op2_tf, op0_tf;
--- 2607,2613 ----
[(set (match_operand:DI 0 "register_operand" "")
(div:DI (match_operand:DI 1 "general_operand" "")
(match_operand:DI 2 "general_operand" "")))]
! "TARGET_80LD && TARGET_INLINE_DIV"
"
{
rtx op1_tf, op2_tf, op0_tf;
***************
*** 2623,2629 ****
[(set (match_operand:DI 0 "register_operand" "")
(mod:SI (match_operand:DI 1 "general_operand" "")
(match_operand:DI 2 "general_operand" "")))]
! "TARGET_INLINE_DIV"
"
{
rtx op2_neg, div;
--- 2637,2643 ----
[(set (match_operand:DI 0 "register_operand" "")
(mod:SI (match_operand:DI 1 "general_operand" "")
(match_operand:DI 2 "general_operand" "")))]
! "TARGET_80LD && TARGET_INLINE_DIV"
"
{
rtx op2_neg, div;
***************
*** 2641,2647 ****
[(set (match_operand:DI 0 "register_operand" "")
(udiv:DI (match_operand:DI 1 "general_operand" "")
(match_operand:DI 2 "general_operand" "")))]
! "TARGET_INLINE_DIV"
"
{
rtx op1_tf, op2_tf, op0_tf;
--- 2655,2661 ----
[(set (match_operand:DI 0 "register_operand" "")
(udiv:DI (match_operand:DI 1 "general_operand" "")
(match_operand:DI 2 "general_operand" "")))]
! "TARGET_80LD && TARGET_INLINE_DIV"
"
{
rtx op1_tf, op2_tf, op0_tf;
***************
*** 2671,2677 ****
[(set (match_operand:DI 0 "register_operand" "")
(umod:DI (match_operand:DI 1 "general_operand" "")
(match_operand:DI 2 "general_operand" "")))]
! "TARGET_INLINE_DIV"
"
{
rtx op2_neg, div;
--- 2685,2691 ----
[(set (match_operand:DI 0 "register_operand" "")
(umod:DI (match_operand:DI 1 "general_operand" "")
(match_operand:DI 2 "general_operand" "")))]
! "TARGET_80LD && TARGET_INLINE_DIV"
"
{
rtx op2_neg, div;
***************
*** 2693,2699 ****
(clobber (match_scratch:TF 4 "=&f"))
(clobber (match_scratch:TF 5 "=&f"))
(clobber (match_scratch:BI 6 "=c"))]
! "TARGET_INLINE_DIV_LAT"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
--- 2707,2713 ----
(clobber (match_scratch:TF 4 "=&f"))
(clobber (match_scratch:TF 5 "=&f"))
(clobber (match_scratch:BI 6 "=c"))]
! "TARGET_80LD && TARGET_INLINE_DIV_LAT"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
***************
*** 2751,2757 ****
(clobber (match_scratch:TF 3 "=&f"))
(clobber (match_scratch:TF 4 "=f"))
(clobber (match_scratch:BI 5 "=c"))]
! "TARGET_INLINE_DIV_THR"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
--- 2765,2771 ----
(clobber (match_scratch:TF 3 "=&f"))
(clobber (match_scratch:TF 4 "=f"))
(clobber (match_scratch:BI 5 "=c"))]
! "TARGET_80LD && TARGET_INLINE_DIV_THR"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
***************
*** 2901,2907 ****
[(set (match_operand:SF 0 "fr_register_operand" "")
(div:SF (match_operand:SF 1 "fr_register_operand" "")
(match_operand:SF 2 "fr_register_operand" "")))]
! "TARGET_INLINE_DIV"
"
{
rtx insn;
--- 2915,2921 ----
[(set (match_operand:SF 0 "fr_register_operand" "")
(div:SF (match_operand:SF 1 "fr_register_operand" "")
(match_operand:SF 2 "fr_register_operand" "")))]
! "TARGET_80LD && TARGET_INLINE_DIV"
"
{
rtx insn;
***************
*** 2920,2926 ****
(clobber (match_scratch:TF 3 "=&f"))
(clobber (match_scratch:TF 4 "=f"))
(clobber (match_scratch:BI 5 "=c"))]
! "TARGET_INLINE_DIV_LAT"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
--- 2934,2940 ----
(clobber (match_scratch:TF 3 "=&f"))
(clobber (match_scratch:TF 4 "=f"))
(clobber (match_scratch:BI 5 "=c"))]
! "TARGET_80LD && TARGET_INLINE_DIV_LAT"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
***************
*** 2974,2980 ****
(clobber (match_scratch:TF 3 "=&f"))
(clobber (match_scratch:TF 4 "=f"))
(clobber (match_scratch:BI 5 "=c"))]
! "TARGET_INLINE_DIV_THR"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
--- 2988,2994 ----
(clobber (match_scratch:TF 3 "=&f"))
(clobber (match_scratch:TF 4 "=f"))
(clobber (match_scratch:BI 5 "=c"))]
! "TARGET_80LD && TARGET_INLINE_DIV_THR"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
***************
*** 3205,3211 ****
[(set (match_operand:DF 0 "fr_register_operand" "")
(div:DF (match_operand:DF 1 "fr_register_operand" "")
(match_operand:DF 2 "fr_register_operand" "")))]
! "TARGET_INLINE_DIV"
"
{
rtx insn;
--- 3219,3225 ----
[(set (match_operand:DF 0 "fr_register_operand" "")
(div:DF (match_operand:DF 1 "fr_register_operand" "")
(match_operand:DF 2 "fr_register_operand" "")))]
! "TARGET_80LD && TARGET_INLINE_DIV"
"
{
rtx insn;
***************
*** 3225,3231 ****
(clobber (match_scratch:TF 4 "=&f"))
(clobber (match_scratch:TF 5 "=&f"))
(clobber (match_scratch:BI 6 "=c"))]
! "TARGET_INLINE_DIV_LAT"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 7) (div:TF (const_int 1) (match_dup 9)))
--- 3239,3245 ----
(clobber (match_scratch:TF 4 "=&f"))
(clobber (match_scratch:TF 5 "=&f"))
(clobber (match_scratch:BI 6 "=c"))]
! "TARGET_80LD && TARGET_INLINE_DIV_LAT"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 7) (div:TF (const_int 1) (match_dup 9)))
***************
*** 3302,3308 ****
(clobber (match_scratch:TF 3 "=&f"))
(clobber (match_scratch:DF 4 "=f"))
(clobber (match_scratch:BI 5 "=c"))]
! "TARGET_INLINE_DIV_THR"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
--- 3316,3322 ----
(clobber (match_scratch:TF 3 "=&f"))
(clobber (match_scratch:DF 4 "=f"))
(clobber (match_scratch:BI 5 "=c"))]
! "TARGET_80LD && TARGET_INLINE_DIV_THR"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
***************
*** 3368,3374 ****
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(plus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
! ""
"fadd %0 = %F1, %F2%B0"
[(set_attr "itanium_class" "fmac")])
--- 3382,3388 ----
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(plus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
! "TARGET_80LD"
"fadd %0 = %F1, %F2%B0"
[(set_attr "itanium_class" "fmac")])
***************
*** 3377,3383 ****
(float_truncate:SF
(plus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
! ""
"fadd.s %0 = %F1, %F2%B0"
[(set_attr "itanium_class" "fmac")])
--- 3391,3397 ----
(float_truncate:SF
(plus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
! "TARGET_80LD"
"fadd.s %0 = %F1, %F2%B0"
[(set_attr "itanium_class" "fmac")])
***************
*** 3386,3392 ****
(float_truncate:DF
(plus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
! ""
"fadd.d %0 = %F1, %F2%B0"
[(set_attr "itanium_class" "fmac")])
--- 3400,3406 ----
(float_truncate:DF
(plus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
! "TARGET_80LD"
"fadd.d %0 = %F1, %F2%B0"
[(set_attr "itanium_class" "fmac")])
***************
*** 3394,3400 ****
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(minus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
! ""
"fsub %0 = %F1, %F2%B0"
[(set_attr "itanium_class" "fmac")])
--- 3408,3414 ----
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(minus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
! "TARGET_80LD"
"fsub %0 = %F1, %F2%B0"
[(set_attr "itanium_class" "fmac")])
***************
*** 3403,3409 ****
(float_truncate:SF
(minus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
! ""
"fsub.s %0 = %F1, %F2%B0"
[(set_attr "itanium_class" "fmac")])
--- 3417,3423 ----
(float_truncate:SF
(minus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
! "TARGET_80LD"
"fsub.s %0 = %F1, %F2%B0"
[(set_attr "itanium_class" "fmac")])
***************
*** 3412,3418 ****
(float_truncate:DF
(minus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
! ""
"fsub.d %0 = %F1, %F2%B0"
[(set_attr "itanium_class" "fmac")])
--- 3426,3432 ----
(float_truncate:DF
(minus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
! "TARGET_80LD"
"fsub.d %0 = %F1, %F2%B0"
[(set_attr "itanium_class" "fmac")])
***************
*** 3420,3426 ****
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
! ""
"fmpy %0 = %F1, %F2%B0"
[(set_attr "itanium_class" "fmac")])
--- 3434,3440 ----
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
! "TARGET_80LD"
"fmpy %0 = %F1, %F2%B0"
[(set_attr "itanium_class" "fmac")])
***************
*** 3429,3435 ****
(float_truncate:SF
(mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
! ""
"fmpy.s %0 = %F1, %F2%B0"
[(set_attr "itanium_class" "fmac")])
--- 3443,3449 ----
(float_truncate:SF
(mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
! "TARGET_80LD"
"fmpy.s %0 = %F1, %F2%B0"
[(set_attr "itanium_class" "fmac")])
***************
*** 3438,3444 ****
(float_truncate:DF
(mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
! ""
"fmpy.d %0 = %F1, %F2%B0"
[(set_attr "itanium_class" "fmac")])
--- 3452,3458 ----
(float_truncate:DF
(mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
! "TARGET_80LD"
"fmpy.d %0 = %F1, %F2%B0"
[(set_attr "itanium_class" "fmac")])
***************
*** 3447,3453 ****
(mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
(use (match_operand:SI 3 "const_int_operand" ""))]
! ""
"fmpy.s%3 %0 = %F1, %F2%B0"
[(set_attr "itanium_class" "fmac")])
--- 3461,3467 ----
(mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
(use (match_operand:SI 3 "const_int_operand" ""))]
! "TARGET_80LD"
"fmpy.s%3 %0 = %F1, %F2%B0"
[(set_attr "itanium_class" "fmac")])
***************
*** 3457,3463 ****
(mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))
(use (match_operand:SI 3 "const_int_operand" ""))]
! ""
"fmpy.s.s%3 %0 = %F1, %F2%B0"
[(set_attr "itanium_class" "fmac")])
--- 3471,3477 ----
(mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))
(use (match_operand:SI 3 "const_int_operand" ""))]
! "TARGET_80LD"
"fmpy.s.s%3 %0 = %F1, %F2%B0"
[(set_attr "itanium_class" "fmac")])
***************
*** 3467,3494 ****
(mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))
(use (match_operand:SI 3 "const_int_operand" ""))]
! ""
"fmpy.d.s%3 %0 = %F1, %F2%B0"
[(set_attr "itanium_class" "fmac")])
(define_insn "abstf2"
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(abs:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")))]
! ""
"fabs %0 = %F1%B0"
[(set_attr "itanium_class" "fmisc")])
(define_insn "negtf2"
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(neg:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")))]
! ""
"fneg %0 = %F1%B0"
[(set_attr "itanium_class" "fmisc")])
(define_insn "*nabstf2"
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(neg:TF (abs:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG"))))]
! ""
"fnegabs %0 = %F1%B0"
[(set_attr "itanium_class" "fmisc")])
--- 3481,3508 ----
(mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))
(use (match_operand:SI 3 "const_int_operand" ""))]
! "TARGET_80LD"
"fmpy.d.s%3 %0 = %F1, %F2%B0"
[(set_attr "itanium_class" "fmac")])
(define_insn "abstf2"
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(abs:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")))]
! "TARGET_80LD"
"fabs %0 = %F1%B0"
[(set_attr "itanium_class" "fmisc")])
(define_insn "negtf2"
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(neg:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")))]
! "TARGET_80LD"
"fneg %0 = %F1%B0"
[(set_attr "itanium_class" "fmisc")])
(define_insn "*nabstf2"
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(neg:TF (abs:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG"))))]
! "TARGET_80LD"
"fnegabs %0 = %F1%B0"
[(set_attr "itanium_class" "fmisc")])
***************
*** 3496,3502 ****
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(smin:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
! ""
"fmin %0 = %F1, %F2%B0"
[(set_attr "itanium_class" "fmisc")])
--- 3510,3516 ----
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(smin:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
! "TARGET_80LD"
"fmin %0 = %F1, %F2%B0"
[(set_attr "itanium_class" "fmisc")])
***************
*** 3504,3510 ****
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(smax:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
! ""
"fmax %0 = %F1, %F2%B0"
[(set_attr "itanium_class" "fmisc")])
--- 3518,3524 ----
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(smax:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
! "TARGET_80LD"
"fmax %0 = %F1, %F2%B0"
[(set_attr "itanium_class" "fmisc")])
***************
*** 3513,3519 ****
(plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))]
! ""
"fma %0 = %F1, %F2, %F3%B0"
[(set_attr "itanium_class" "fmac")])
--- 3527,3533 ----
(plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))]
! "TARGET_80LD"
"fma %0 = %F1, %F2, %F3%B0"
[(set_attr "itanium_class" "fmac")])
***************
*** 3523,3529 ****
(plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
! ""
"fma.s %0 = %F1, %F2, %F3%B0"
[(set_attr "itanium_class" "fmac")])
--- 3537,3543 ----
(plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
! "TARGET_80LD"
"fma.s %0 = %F1, %F2, %F3%B0"
[(set_attr "itanium_class" "fmac")])
***************
*** 3533,3539 ****
(plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
! ""
"fma.d %0 = %F1, %F2, %F3%B0"
[(set_attr "itanium_class" "fmac")])
--- 3547,3553 ----
(plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
! "TARGET_80LD"
"fma.d %0 = %F1, %F2, %F3%B0"
[(set_attr "itanium_class" "fmac")])
***************
*** 3543,3549 ****
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))
(use (match_operand:SI 4 "const_int_operand" ""))]
! ""
"fma.s%4 %0 = %F1, %F2, %F3%B0"
[(set_attr "itanium_class" "fmac")])
--- 3557,3563 ----
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))
(use (match_operand:SI 4 "const_int_operand" ""))]
! "TARGET_80LD"
"fma.s%4 %0 = %F1, %F2, %F3%B0"
[(set_attr "itanium_class" "fmac")])
***************
*** 3554,3560 ****
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))
(use (match_operand:SI 4 "const_int_operand" ""))]
! ""
"fma.d.s%4 %0 = %F1, %F2, %F3%B0"
[(set_attr "itanium_class" "fmac")])
--- 3568,3574 ----
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))
(use (match_operand:SI 4 "const_int_operand" ""))]
! "TARGET_80LD"
"fma.d.s%4 %0 = %F1, %F2, %F3%B0"
[(set_attr "itanium_class" "fmac")])
***************
*** 3563,3569 ****
(minus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))]
! ""
"fms %0 = %F1, %F2, %F3%B0"
[(set_attr "itanium_class" "fmac")])
--- 3577,3583 ----
(minus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))]
! "TARGET_80LD"
"fms %0 = %F1, %F2, %F3%B0"
[(set_attr "itanium_class" "fmac")])
***************
*** 3573,3579 ****
(minus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
! ""
"fms.s %0 = %F1, %F2, %F3%B0"
[(set_attr "itanium_class" "fmac")])
--- 3587,3593 ----
(minus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
! "TARGET_80LD"
"fms.s %0 = %F1, %F2, %F3%B0"
[(set_attr "itanium_class" "fmac")])
***************
*** 3583,3589 ****
(minus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
! ""
"fms.d %0 = %F1, %F2, %F3%B0"
[(set_attr "itanium_class" "fmac")])
--- 3597,3603 ----
(minus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
! "TARGET_80LD"
"fms.d %0 = %F1, %F2, %F3%B0"
[(set_attr "itanium_class" "fmac")])
***************
*** 3591,3597 ****
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(neg:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
! ""
"fnmpy %0 = %F1, %F2%B0"
[(set_attr "itanium_class" "fmac")])
--- 3605,3611 ----
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(neg:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
! "TARGET_80LD"
"fnmpy %0 = %F1, %F2%B0"
[(set_attr "itanium_class" "fmac")])
***************
*** 3601,3607 ****
(neg:TF (mult:TF
(match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))))]
! ""
"fnmpy.s %0 = %F1, %F2%B0"
[(set_attr "itanium_class" "fmac")])
--- 3615,3621 ----
(neg:TF (mult:TF
(match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))))]
! "TARGET_80LD"
"fnmpy.s %0 = %F1, %F2%B0"
[(set_attr "itanium_class" "fmac")])
***************
*** 3611,3617 ****
(neg:TF (mult:TF
(match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))))]
! ""
"fnmpy.d %0 = %F1, %F2%B0"
[(set_attr "itanium_class" "fmac")])
--- 3625,3631 ----
(neg:TF (mult:TF
(match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))))]
! "TARGET_80LD"
"fnmpy.d %0 = %F1, %F2%B0"
[(set_attr "itanium_class" "fmac")])
***************
*** 3623,3629 ****
(match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))]
! ""
"fnma %0 = %F1, %F2, %F3%B0"
[(set_attr "itanium_class" "fmac")])
--- 3637,3643 ----
(match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))]
! "TARGET_80LD"
"fnma %0 = %F1, %F2, %F3%B0"
[(set_attr "itanium_class" "fmac")])
***************
*** 3634,3640 ****
(match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
! ""
"fnma.s %0 = %F1, %F2, %F3%B0"
[(set_attr "itanium_class" "fmac")])
--- 3648,3654 ----
(match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
! "TARGET_80LD"
"fnma.s %0 = %F1, %F2, %F3%B0"
[(set_attr "itanium_class" "fmac")])
***************
*** 3645,3651 ****
(match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
! ""
"fnma.d %0 = %F1, %F2, %F3%B0"
[(set_attr "itanium_class" "fmac")])
--- 3659,3665 ----
(match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
! "TARGET_80LD"
"fnma.d %0 = %F1, %F2, %F3%B0"
[(set_attr "itanium_class" "fmac")])
***************
*** 3656,3662 ****
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))
(use (match_operand:SI 4 "const_int_operand" ""))]
! ""
"fnma.s%4 %0 = %F1, %F2, %F3%B0"
[(set_attr "itanium_class" "fmac")])
--- 3670,3676 ----
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))
(use (match_operand:SI 4 "const_int_operand" ""))]
! "TARGET_80LD"
"fnma.s%4 %0 = %F1, %F2, %F3%B0"
[(set_attr "itanium_class" "fmac")])
***************
*** 3669,3675 ****
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))
(use (match_operand:SI 4 "const_int_operand" ""))]
! ""
"fnma.d.s%4 %0 = %F1, %F2, %F3%B0"
[(set_attr "itanium_class" "fmac")])
--- 3683,3689 ----
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))
(use (match_operand:SI 4 "const_int_operand" ""))]
! "TARGET_80LD"
"fnma.d.s%4 %0 = %F1, %F2, %F3%B0"
[(set_attr "itanium_class" "fmac")])
***************
*** 3677,3683 ****
[(set (match_operand:TF 0 "fr_register_operand" "")
(div:TF (match_operand:TF 1 "fr_register_operand" "")
(match_operand:TF 2 "fr_register_operand" "")))]
! "TARGET_INLINE_DIV"
"
{
rtx insn;
--- 3691,3697 ----
[(set (match_operand:TF 0 "fr_register_operand" "")
(div:TF (match_operand:TF 1 "fr_register_operand" "")
(match_operand:TF 2 "fr_register_operand" "")))]
! "TARGET_80LD && TARGET_INLINE_DIV"
"
{
rtx insn;
***************
*** 3698,3704 ****
(clobber (match_scratch:TF 5 "=&f"))
(clobber (match_scratch:TF 6 "=&f"))
(clobber (match_scratch:BI 7 "=c"))]
! "TARGET_INLINE_DIV_LAT"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
--- 3712,3718 ----
(clobber (match_scratch:TF 5 "=&f"))
(clobber (match_scratch:TF 6 "=&f"))
(clobber (match_scratch:BI 7 "=c"))]
! "TARGET_80LD && TARGET_INLINE_DIV_LAT"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
***************
*** 3775,3781 ****
(clobber (match_scratch:TF 3 "=&f"))
(clobber (match_scratch:TF 4 "=&f"))
(clobber (match_scratch:BI 5 "=c"))]
! "TARGET_INLINE_DIV_THR"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
--- 3789,3795 ----
(clobber (match_scratch:TF 3 "=&f"))
(clobber (match_scratch:TF 4 "=&f"))
(clobber (match_scratch:BI 5 "=c"))]
! "TARGET_80LD && TARGET_INLINE_DIV_THR"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
***************
*** 3855,3861 ****
(unspec:BI [(match_operand:TF 2 "fr_register_operand" "f")
(match_dup 3)] 5))
(use (match_operand:SI 4 "const_int_operand" ""))]
! ""
"frcpa.s%4 %0, %1 = %2, %3"
[(set_attr "itanium_class" "fmisc")
(set_attr "predicable" "no")])
--- 3869,3875 ----
(unspec:BI [(match_operand:TF 2 "fr_register_operand" "f")
(match_dup 3)] 5))
(use (match_operand:SI 4 "const_int_operand" ""))]
! "TARGET_80LD"
"frcpa.s%4 %0, %1 = %2, %3"
[(set_attr "itanium_class" "fmisc")
(set_attr "predicable" "no")])
***************
*** 3898,3904 ****
[(set (match_operand:SI 0 "gr_register_operand" "")
(ashiftrt:SI (match_operand:SI 1 "gr_register_operand" "")
(match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
! ""
"
{
rtx subtarget = gen_reg_rtx (DImode);
--- 3912,3918 ----
[(set (match_operand:SI 0 "gr_register_operand" "")
(ashiftrt:SI (match_operand:SI 1 "gr_register_operand" "")
(match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
! "! TARGET_HPUX"
"
{
rtx subtarget = gen_reg_rtx (DImode);
***************
*** 3920,3926 ****
[(set (match_operand:SI 0 "gr_register_operand" "")
(lshiftrt:SI (match_operand:SI 1 "gr_register_operand" "")
(match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
! ""
"
{
rtx subtarget = gen_reg_rtx (DImode);
--- 3934,3940 ----
[(set (match_operand:SI 0 "gr_register_operand" "")
(lshiftrt:SI (match_operand:SI 1 "gr_register_operand" "")
(match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
! "! TARGET_HPUX"
"
{
rtx subtarget = gen_reg_rtx (DImode);
***************
*** 4266,4272 ****
[(set (cc0)
(compare (match_operand:TF 0 "tfreg_or_fp01_operand" "")
(match_operand:TF 1 "tfreg_or_fp01_operand" "")))]
! ""
"
{
ia64_compare_op0 = operands[0];
--- 4280,4286 ----
[(set (cc0)
(compare (match_operand:TF 0 "tfreg_or_fp01_operand" "")
(match_operand:TF 1 "tfreg_or_fp01_operand" "")))]
! "TARGET_80LD"
"
{
ia64_compare_op0 = operands[0];
***************
*** 4339,4345 ****
(match_operator:BI 1 "comparison_operator"
[(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG")]))]
! ""
"fcmp.%D1 %0, %I0 = %F2, %F3"
[(set_attr "itanium_class" "fcmp")])
--- 4353,4359 ----
(match_operator:BI 1 "comparison_operator"
[(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG")]))]
! "TARGET_80LD"
"fcmp.%D1 %0, %I0 = %F2, %F3"
[(set_attr "itanium_class" "fcmp")])
***************
*** 4351,4357 ****
(const_int 1)
(match_operand:DI 2 "immediate_operand" "n"))
(const_int 0)))]
! ""
"tbit.z %0, %I0 = %1, %2"
[(set_attr "itanium_class" "tbit")])
--- 4365,4371 ----
(const_int 1)
(match_operand:DI 2 "immediate_operand" "n"))
(const_int 0)))]
! "! TARGET_HPUX"
"tbit.z %0, %I0 = %1, %2"
[(set_attr "itanium_class" "tbit")])
***************
*** 4361,4367 ****
(const_int 1)
(match_operand:DI 2 "immediate_operand" "n"))
(const_int 0)))]
! ""
"tbit.nz %0, %I0 = %1, %2"
[(set_attr "itanium_class" "tbit")])
--- 4375,4381 ----
(const_int 1)
(match_operand:DI 2 "immediate_operand" "n"))
(const_int 0)))]
! "! TARGET_HPUX"
"tbit.nz %0, %I0 = %1, %2"
[(set_attr "itanium_class" "tbit")])
***************
*** 5481,5486 ****
--- 5495,5514 ----
""
"xchg8 %0 = %1, %2"
[(set_attr "itanium_class" "sem")])
+
+
+ ;;
+ ;;
+ ;; UNSPEC instruction definition to "swizzle" 32 bit pointer into 64 bit
+ ;; pointer.
+
+ (define_insn "extend_ptr"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (unspec:DI [(match_operand:SI 1 "register_operand" "r")] 24))]
+ ""
+ "addp4 %0 = 0,%1"
+ [(set_attr "type" "I")])
+
;; Predication.
*** config/ia64/hpux.h@@/main/LATEST Tue Dec 12 12:54:13 2000
--- config/ia64/hpux.h Mon Dec 18 09:07:15 2000
***************
*** 0 ****
--- 1,224 ----
+ /* Definitions for ia64-hpux target. */
+ #include "ia64/ia64.h"
+ #include "svr4.h"
+ #include "sysv4.h"
+
+ /* Turn this off so we get true 128 bit long doubles. In theory removing
+ the undef should allow a compiler that uses INTEL_EXTENDED_IEEE_FORMAT
+ for long double to be built. */
+
+ #undef INTEL_EXTENDED_IEEE_FORMAT
+
+ #ifndef INTEL_EXTENDED_IEEE_FORMAT
+ #include "hpux_longdouble.h"
+ #undef TARGET_80LD
+ #define TARGET_80LD 0
+ #endif
+
+ /* ??? We say that CCmode values require two registers. This allows us to
+ easily store the normal and inverted values. We use CCImode to indicate
+ a single predicate register. */
+
+ #undef HARD_REGNO_NREGS
+ #if (LONG_DOUBLE_TYPE_SIZE == 128) && !defined(INTEL_EXTENDED_IEEE_FORMAT)
+ #define HARD_REGNO_NREGS(REGNO, MODE) \
+ ((REGNO) == PR_REG (0) && (MODE) == DImode ? 64 \
+ : PR_REGNO_P (REGNO) && (MODE) == CCmode ? 2 \
+ : PR_REGNO_P (REGNO) && (MODE) == CCImode ? 1 \
+ : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
+ #else
+ #define HARD_REGNO_NREGS(REGNO, MODE) \
+ ((REGNO) == PR_REG (0) && (MODE) == DImode ? 64 \
+ : PR_REGNO_P (REGNO) && (MODE) == CCmode ? 2 \
+ : PR_REGNO_P (REGNO) && (MODE) == CCImode ? 1 \
+ : FR_REGNO_P (REGNO) && (MODE) == TFmode ? 1 \
+ : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
+ #endif
+
+ /* A C expression that is nonzero if it is permissible to store a value of mode
+ MODE in hard register number REGNO (or in several registers starting with
+ that one). */
+
+ #undef HARD_REGNO_MODE_OK
+ #if LONG_DOUBLE_TYPE_SIZE == 128 && !defined(INTEL_EXTENDED_IEEE_FORMAT)
+ #define HARD_REGNO_MODE_OK(REGNO, MODE) \
+ (FR_REGNO_P (REGNO) ? GET_MODE_CLASS (MODE) != MODE_CC && (MODE) != TImode \
+ && (MODE) != TFmode \
+ : PR_REGNO_P (REGNO) ? \
+ (MODE) == BImode || GET_MODE_CLASS (MODE) == MODE_CC \
+ : GR_REGNO_P (REGNO) ? (MODE) != CCImode \
+ : AR_REGNO_P (REGNO) ? (MODE) == DImode \
+ : BR_REGNO_P (REGNO) ? (MODE) == DImode \
+ : 0)
+ #else
+ #define HARD_REGNO_MODE_OK(REGNO, MODE) \
+ (FR_REGNO_P (REGNO) ? GET_MODE_CLASS (MODE) != MODE_CC && (MODE) != TImode \
+ : PR_REGNO_P (REGNO) ? \
+ (MODE) == BImode || GET_MODE_CLASS (MODE) == MODE_CC \
+ : GR_REGNO_P (REGNO) ? (MODE) != CCImode && (MODE) != TFmode \
+ : AR_REGNO_P (REGNO) ? (MODE) == DImode \
+ : BR_REGNO_P (REGNO) ? (MODE) == DImode \
+ : 0)
+ #endif
+
+ #undef LIBCALL_VALUE
+ #if LONG_DOUBLE_TYPE_SIZE == 128 && !defined(INTEL_EXTENDED_IEEE_FORMAT)
+ #define LIBCALL_VALUE(MODE) \
+ gen_rtx_REG (MODE, \
+ ((((GET_MODE_CLASS (MODE) == MODE_FLOAT \
+ || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)) \
+ && (MODE != TFmode)) \
+ ? FR_RET_FIRST : GR_RET_FIRST))
+ #else
+ #define LIBCALL_VALUE(MODE) \
+ gen_rtx_REG (MODE, \
+ ((GET_MODE_CLASS (MODE) == MODE_FLOAT \
+ || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
+ ? FR_RET_FIRST : GR_RET_FIRST))
+ #endif
+
+
+ #undef SUBTARGET_SWITCHES
+ #define SUBTARGET_SWITCHES \
+ { "ilp32", MASK_ILP32, "Generate ILP32 code" }, \
+ { "lp64", -MASK_ILP32, "Generate LP64 code" },
+
+ /* -D__fpreg=long double is needed to compensate for
+ the lack of __fpreg which is a primative type in
+ HP C but does not exist in GNU C.
+ */
+
+ #undef CPP_PREDEFINES
+ #define CPP_PREDEFINES "\
+ -D__IA64__ -D__ia64 -D__ia64__ -D__hpux -D__hpux__ -Dhpux -Dunix \
+ -D_HPUX_SOURCE -D__STDC_EXT__ -D__BIG_ENDIAN__ -D_LONGLONG -D__ELF__ \
+ -Asystem(hpux) -Acpu(ia64) -Amachine(ia64) -D_UINT128_T"
+
+ #undef CPP_SPEC
+ #define CPP_SPEC \
+ "%{mcpu=itanium:-D__itanium__} %{mbig-endian:-D__BIG_ENDIAN__} \
+ %{!milp32:-D__LP64__ -D__LONG_MAX__=9223372036854775807L} \
+ -D__fpreg=long\\ double \
+ -D__float80=long\\ double \
+ -D__float128=long\\ double"
+
+ /* GCC assumes you are using /usr/lib (or the equivelent) for the
+ default libs and then adding an extra directory name like hpux32
+ to make /usr/lib/hpux32 for non-default cases. If the default
+ case does not go in /usr/lib but has its own subdirectory name
+ (like /usr/lib/hpux64), give the subname here.
+ */
+
+ #define MULTILIB_DEFAULT_SUBDIR "hpux64"
+
+ /* ASM_SPEC may need to be extended to include the standard svr4 assembler
+ options, but it also needs to pass on the -milp32 flag if used. */
+
+ #undef ASM_SPEC
+ #define ASM_SPEC "%{milp32:-milp32}"
+
+ /* Define this for shared library support because it isn't in the main
+ hpux.h file. */
+
+ #undef STARTFILE_SPEC
+ #undef ENDFILE_SPEC
+
+ /* We used to define -funwind-tables here but that is done automatically now
+ by code added by cygnus. */
+
+ #undef CC1_SPEC
+ #define CC1_SPEC "-ma-step"
+
+ #undef CC1PLUS_SPEC
+ #define CC1PLUS_SPEC "-ma-step"
+
+ #ifdef CROSS_COMPILE
+ #define STARTFILE_SPEC "%{!shared:crt0%O%s}"
+ #else
+ #define STARTFILE_SPEC "/usr/ccs/lib/%{milp32:hpux32}%{!milp32:hpux64}/crt0%O"
+ #endif
+
+ #undef LINK_SPEC
+ #define LINK_SPEC "\
+ +Accept TypeMismatch \
+ %{shared:-b} \
+ %{!shared: \
+ -u main \
+ %{!static: \
+ %{rdynamic:-export-dynamic}} \
+ %{static:-static}}"
+
+ #undef LIB_SPEC
+ #define LIB_SPEC "%{!shared:%{!symbolic:-lc}}"
+
+ #define DONT_USE_BUILTIN_SETJMP
+ #define JMP_BUF_SIZE (8 * 76)
+
+ #undef ASM_FILE_END /* no ident */
+
+ #undef CONST_SECTION_ASM_OP
+ #define CONST_SECTION_ASM_OP "\t.section\t.data,\t\"a\",\t\"progbits\""
+
+ #undef BITS_BIG_ENDIAN
+ #define BITS_BIG_ENDIAN 1
+
+ #undef TARGET_DEFAULT
+ #define TARGET_DEFAULT (MASK_DWARF2_ASM | MASK_BIG_ENDIAN)
+
+ /* This doesn't compile in the native compiler, lets try turning it off. */
+
+ #undef DBX_DEBUGGING_INFO
+
+ /*
+ * We need this macro to output DWARF2 information correctly. The macro
+ * is defined in dwarf2out.c, but it will not do section relative offsets
+ * which messes up our ability to debug using gdb.
+ */
+
+ #undef ASM_OUTPUT_DWARF_OFFSET
+ #define ASM_OUTPUT_DWARF_OFFSET(FILE,LABEL) \
+ do { fprintf ((FILE), "\t%s\t", UNALIGNED_OFFSET_ASM_OP); \
+ fprintf ((FILE), "@secrel("); \
+ assemble_name (FILE, LABEL); \
+ fprintf ((FILE), ")"); \
+ } while (0)
+
+ /* Minimum number of storage units in a word; normally 4. */
+ /* If I don't define this it defaults to UNITS_PER_WORD and then libgcc2.c */
+ /* does not build. */
+
+ #define MIN_UNITS_PER_WORD 4
+
+ /*
+ * This will ensure that structures passed in registers have values aligned
+ * to the left. This is done by stopping some of the code that deals with
+ * function calls from padding the structure values so that everything is
+ * aligned to the right. We have to do this because of the runtime
+ * architecture specified for HP-UX on IA64 requires that structure values
+ * passed in registers be aligned to the left.
+ */
+
+ #define NO_PAD_REG_STRUCT_PARMS 1
+
+ /* A C expression whose value is zero if pointers that need to be extended
+ * from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and
+ * nonzero if they are zero-extended.
+ *
+ * If there is a extend_ptr instruction (HAVE_extend_ptr is defined) then
+ * it doesn't matter what POINTERS_EXTEND_UNSIGNED is set to as long as
+ * it is defined.
+ */
+
+ #define POINTERS_EXTEND_UNSIGNED -1
+
+ /*
+ * Defined so that some of the instructions in the ia64.md file will
+ * not be generated by the compiler. In particular, these are
+ * extzv, extv, and insv which are not coded correctly in expmed.c
+ * for store_bit_field() and extract_bit_field() for big-endian.
+ */
+
+ #undef TARGET_HPUX
+ #define TARGET_HPUX 1
+
+ /* End of hpux.h */
*** config/ia64/hpux_longdouble.h@@/main/LATEST Tue Dec 12 12:55:03 2000
--- config/ia64/hpux_longdouble.h Tue Jan 9 11:58:43 2001
***************
*** 0 ****
--- 1,97 ----
+ /* Definitions of long double support for GNU compiler.
+ Copyright (C) 2000 Free Software Foundation, Inc.
+
+ This file is part of GNU CC.
+
+ GNU CC is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2, or (at your option)
+ any later version.
+
+ GNU CC is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GNU CC; see the file COPYING. If not, write to
+ the Free Software Foundation, 59 Temple Place - Suite 330,
+ Boston, MA 02111-1307, USA. */
+
+ /* Define library calls for quad FP operations. These are all part of the
+ PA32 and PA64 ABIs. */
+ #define ADDTF3_LIBCALL "_U_Qfadd"
+ #define SUBTF3_LIBCALL "_U_Qfsub"
+ #define MULTF3_LIBCALL "_U_Qfmpy"
+ #define DIVTF3_LIBCALL "_U_Qfdiv"
+ #define NEGTF2_LIBCALL "_U_Qfneg"
+ #define ABSTF2_LIBCALL "_U_Qfabs"
+ #define SMINTF3_LIBCALL "_U_Qfmin"
+ #define SMAXTF3_LIBCALL "_U_Qfmax"
+ #define EXTENDSFTF2_LIBCALL "_U_Qfcnvff_sgl_to_quad"
+ #define EXTENDDFTF2_LIBCALL "_U_Qfcnvff_dbl_to_quad"
+ #define TRUNCTFSF2_LIBCALL "_U_Qfcnvff_quad_to_sgl"
+ #define TRUNCTFDF2_LIBCALL "_U_Qfcnvff_quad_to_dbl"
+ #define FLOATSITF2_LIBCALL "_U_Qfcnvxf_sgl_to_quad"
+ #define FLOATDITF2_LIBCALL "_U_Qfcnvxf_dbl_to_quad"
+ #define FIX_TRUNCTFSI2_LIBCALL "_U_Qfcnvfxt_quad_to_sgl"
+ #define FIX_TRUNCTFDI2_LIBCALL "_U_Qfcnvfxt_quad_to_dbl"
+ #define EQTF2_LIBCALL "_U_Qfeq"
+ #define NETF2_LIBCALL "_U_Qfne"
+ #define GTTF2_LIBCALL "_U_Qfgt"
+ #define GETF2_LIBCALL "_U_Qfge"
+ #define LTTF2_LIBCALL "_U_Qflt"
+ #define LETF2_LIBCALL "_U_Qfle"
+
+
+ #undef INIT_TARGET_OPTABS
+ #define INIT_TARGET_OPTABS \
+ do { \
+ add_optab->handlers[(int) TFmode].libfunc \
+ = gen_rtx_SYMBOL_REF (Pmode, ADDTF3_LIBCALL); \
+ sub_optab->handlers[(int) TFmode].libfunc \
+ = gen_rtx_SYMBOL_REF (Pmode, SUBTF3_LIBCALL); \
+ smul_optab->handlers[(int) TFmode].libfunc \
+ = gen_rtx_SYMBOL_REF (Pmode, MULTF3_LIBCALL); \
+ flodiv_optab->handlers[(int) TFmode].libfunc \
+ = gen_rtx_SYMBOL_REF (Pmode, DIVTF3_LIBCALL); \
+ smin_optab->handlers[(int) TFmode].libfunc \
+ = gen_rtx_SYMBOL_REF (Pmode, SMINTF3_LIBCALL); \
+ smax_optab->handlers[(int) TFmode].libfunc \
+ = gen_rtx_SYMBOL_REF (Pmode, SMAXTF3_LIBCALL); \
+ abs_optab->handlers[(int) TFmode].libfunc \
+ = gen_rtx_SYMBOL_REF (Pmode, ABSTF2_LIBCALL); \
+ neg_optab->handlers[(int) TFmode].libfunc \
+ = gen_rtx_SYMBOL_REF (Pmode, NEGTF2_LIBCALL); \
+ extendsftf2_libfunc = gen_rtx_SYMBOL_REF (Pmode, EXTENDSFTF2_LIBCALL); \
+ extenddftf2_libfunc = gen_rtx_SYMBOL_REF (Pmode, EXTENDDFTF2_LIBCALL); \
+ trunctfsf2_libfunc = gen_rtx_SYMBOL_REF (Pmode, TRUNCTFSF2_LIBCALL); \
+ trunctfdf2_libfunc = gen_rtx_SYMBOL_REF (Pmode, TRUNCTFDF2_LIBCALL); \
+ floatsitf_libfunc = gen_rtx_SYMBOL_REF (Pmode, FLOATSITF2_LIBCALL); \
+ floatditf_libfunc = gen_rtx_SYMBOL_REF (Pmode, FLOATDITF2_LIBCALL); \
+ fixtfsi_libfunc = gen_rtx_SYMBOL_REF (Pmode, FIX_TRUNCTFSI2_LIBCALL);\
+ fixtfdi_libfunc = gen_rtx_SYMBOL_REF (Pmode, FIX_TRUNCTFDI2_LIBCALL);\
+ fixunstfsi_libfunc = gen_rtx_SYMBOL_REF (Pmode, FIX_TRUNCTFSI2_LIBCALL); \
+ fixunstfdi_libfunc = gen_rtx_SYMBOL_REF (Pmode, FIX_TRUNCTFDI2_LIBCALL); \
+ eqtf2_libfunc = gen_rtx_SYMBOL_REF (Pmode, EQTF2_LIBCALL); \
+ netf2_libfunc = gen_rtx_SYMBOL_REF (Pmode, NETF2_LIBCALL); \
+ gttf2_libfunc = gen_rtx_SYMBOL_REF (Pmode, GTTF2_LIBCALL); \
+ getf2_libfunc = gen_rtx_SYMBOL_REF (Pmode, GETF2_LIBCALL); \
+ lttf2_libfunc = gen_rtx_SYMBOL_REF (Pmode, LTTF2_LIBCALL); \
+ letf2_libfunc = gen_rtx_SYMBOL_REF (Pmode, LETF2_LIBCALL); \
+ \
+ sdiv_optab->handlers[(int) SImode].libfunc = 0; \
+ udiv_optab->handlers[(int) SImode].libfunc = 0; \
+ smod_optab->handlers[(int) SImode].libfunc = 0; \
+ umod_optab->handlers[(int) SImode].libfunc = 0; \
+ \
+ INIT_SUBTARGET_OPTABS; \
+ } while (0)
+
+ /* This is meant to be redefined in the host dependent files */
+ #define INIT_SUBTARGET_OPTABS
+
+ /* Nonzero if a floating point comparison library call for
+ mode MODE that will return a boolean value. Zero if one
+ of the libgcc2 functions is used. */
+ #define FLOAT_LIB_COMPARE_RETURNS_BOOL(MODE, COMPARISON) ((MODE) == TFmode)
*** config/ia64/quadlib.c@@/main/LATEST Tue Dec 12 12:55:50 2000
--- config/ia64/quadlib.c Tue Jan 9 11:58:58 2001
***************
*** 0 ****
--- 1,82 ----
+ /* Subroutines for long double support.
+ Copyright (C) 2000 Free Software Foundation, Inc.
+
+ This file is part of GNU CC.
+
+ GNU CC is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2, or (at your option)
+ any later version.
+
+ In addition to the permissions in the GNU General Public License, the
+ Free Software Foundation gives you unlimited permission to link the
+ compiled version of this file into combinations with other programs,
+ and to distribute those combinations without any restriction coming
+ from the use of this file. (The General Public License restrictions
+ do apply in other respects; for example, they cover modification of
+ the file, and distribution when not linked into a combine
+ executable.)
+
+ GNU CC is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GNU CC; see the file COPYING. If not, write to
+ the Free Software Foundation, 59 Temple Place - Suite 330,
+ Boston, MA 02111-1307, USA. */
+
+ int _U_Qfcmp (long double a, long double b, int);
+ long _U_Qfcnvfxt_quad_to_sgl (long double);
+
+ int
+ _U_Qfeq (long double a, long double b)
+ {
+ return (_U_Qfcmp (a, b, 4) != 0);
+ }
+
+ int
+ _U_Qfne (long double a, long double b)
+ {
+ return (_U_Qfcmp (a, b, 4) == 0);
+ }
+
+ int
+ _U_Qfgt (long double a, long double b)
+ {
+ return (_U_Qfcmp (a, b, 17) != 0);
+ }
+
+ int
+ _U_Qfge (long double a, long double b)
+ {
+ return (_U_Qfcmp (a, b, 21) != 0);
+ }
+
+ int
+ _U_Qflt (long double a, long double b)
+ {
+ return (_U_Qfcmp (a, b, 9) != 0);
+ }
+
+ int
+ _U_Qfle (long double a, long double b)
+ {
+ return (_U_Qfcmp (a, b, 13) != 0);
+ }
+
+ int
+ _U_Qfcomp (long double a, long double b)
+ {
+ if (_U_Qfcmp (a, b, 4) == 0)
+ return 0;
+
+ return (_U_Qfcmp (a, b, 22) != 0 ? 1 : -1);
+ }
+
+ long double
+ _U_Qfneg (long double a)
+ {
+ return (0.0L - a);
+ }
*** config/ia64/t-hpux@@/main/LATEST Tue Jan 9 12:46:26 2001
--- config/ia64/t-hpux Tue Jan 9 12:46:25 2001
***************
*** 0 ****
--- 1,84 ----
+ # Name of assembly file containing libgcc1 functions.
+ # This entry must be present, but it can be empty if the target does
+ # not need any assembler functions to support its code generation.
+ CROSS_LIBGCC1 = libgcc1-asm.a
+ LIBGCC1 = libgcc1-asm.a
+ LIB1ASMSRC = ia64/lib1funcs.asm
+
+ # We get an undefined main when building a cross compiler because our
+ # linkspec has "-u main" and we want that for linking but it makes
+ # LIBGCC1_TEST fail because it uses -nostdlib -nostartup.
+
+ LIBGCC1_TEST =
+
+ # ??? We change the names of the DImode div/mod files so that they won't
+ # accidentally be overridden by libgcc2.c files. We used to use __ia64 as
+ # a prefix, now we use __ as the prefix.
+ LIB1ASMFUNCS = __divtf3 __divdf3 __divsf3 \
+ __divdi3 __moddi3 __udivdi3 __umoddi3 \
+ __divsi3 __modsi3 __udivsi3 __umodsi3 __save_stack_nonlocal \
+ __nonlocal_goto __restore_stack_nonlocal __trampoline
+
+ # ??? Hack to get -P option used when compiling lib1funcs.asm, because Intel
+ # assembler does not accept # line number as a comment.
+ # ??? This breaks C++ pragma interface/implementation, which is used in the
+ # C++ part of libgcc2, hence it had to be disabled. Must find some other way
+ # to support the Intel assembler.
+ #LIBGCC2_DEBUG_CFLAGS = -g1 -P
+
+ SHLIB_MAPFILES += $(srcdir)/config/ia64/libgcc-ia64.ver
+
+ # For svr4 we build crtbegin.o and crtend.o which serve to add begin and
+ # end labels to the .ctors and .dtors section when we link using gcc.
+
+ EXTRA_PARTS=hpux64/crtbegin.o hpux64/crtend.o \
+ hpux64/crtbeginS.o hpux64/crtendS.o \
+ hpux32/crtbegin.o hpux32/crtend.o \
+ hpux32/crtbeginS.o hpux32/crtendS.o
+
+ # Effectively disable the crtbegin/end rules using crtstuff.c
+ T = disable
+
+ LIB2FUNCS_EXTRA=quadlib.c
+
+ quadlib.c: $(srcdir)/config/pa/quadlib.c
+ rm -f quadlib.c
+ cp $(srcdir)/config/pa/quadlib.c .
+
+ # Assemble startup files.
+ hpux-dirs:
+ -if [ -d hpux64 ] ; then true ; else mkdir hpux64; chmod a+rx hpux64; fi
+ -if [ -d hpux32 ] ; then true ; else mkdir hpux32; chmod a+rx hpux32; fi
+ hpux64/crtbegin.o: $(srcdir)/config/ia64/crtbegin.asm $(GCC_PASSES) hpux-dirs
+ $(GCC_FOR_TARGET) -c -o hpux64/crtbegin.o -x assembler-with-cpp $(srcdir)/config/ia64/crtbegin.asm
+ hpux64/crtend.o: $(srcdir)/config/ia64/crtend.asm $(GCC_PASSES) hpux-dirs
+ $(GCC_FOR_TARGET) -c -o hpux64/crtend.o -x assembler-with-cpp $(srcdir)/config/ia64/crtend.asm
+ hpux64/crtbeginS.o: $(srcdir)/config/ia64/crtbegin.asm $(GCC_PASSES) hpux-dirs
+ $(GCC_FOR_TARGET) -DSHARED -c -o hpux64/crtbeginS.o -x assembler-with-cpp $(srcdir)/config/ia64/crtbegin.asm
+ hpux64/crtendS.o: $(srcdir)/config/ia64/crtend.asm $(GCC_PASSES) hpux-dirs
+ $(GCC_FOR_TARGET) -DSHARED -c -o hpux64/crtendS.o -x assembler-with-cpp $(srcdir)/config/ia64/crtend.asm
+
+ hpux32/crtbegin.o: $(srcdir)/config/ia64/crtbegin.asm $(GCC_PASSES) hpux-dirs
+ $(GCC_FOR_TARGET) -milp32 -c -o hpux32/crtbegin.o -x assembler-with-cpp $(srcdir)/config/ia64/crtbegin.asm
+ hpux32/crtend.o: $(srcdir)/config/ia64/crtend.asm $(GCC_PASSES) hpux-dirs
+ $(GCC_FOR_TARGET) -milp32 -c -o hpux32/crtend.o -x assembler-with-cpp $(srcdir)/config/ia64/crtend.asm
+ hpux32/crtbeginS.o: $(srcdir)/config/ia64/crtbegin.asm $(GCC_PASSES) hpux-dirs
+ $(GCC_FOR_TARGET) -DSHARED -milp32 -c -o hpux32/crtbeginS.o -x assembler-with-cpp $(srcdir)/config/ia64/crtbegin.asm
+ hpux32/crtendS.o: $(srcdir)/config/ia64/crtend.asm $(GCC_PASSES) hpux-dirs
+ $(GCC_FOR_TARGET) -DSHARED -milp32 -c -o hpux32/crtendS.o -x assembler-with-cpp $(srcdir)/config/ia64/crtend.asm
+
+ EXTRA_HEADERS = $(srcdir)/config/ia64/ia64intrin.h
+ LIB2ADDEH = $(srcdir)/config/ia64/frame-ia64.c
+
+ # This is to handle the HP-UX ILP32/LP64 dual mode compiler.
+ # MULTILIB_REDUNDANT_DIRS is a cygnus-ism but it handles the
+ # issue of their not being "standard" /usr/lib and a "different"
+ # /usr/lib/hpux64, but rather a /usr/lib/hpux32 and a /usr/lib/hpux64.
+ # If we change the default compilation mode we need to change
+ # MULTILIB_REDUNDANT_DIRS to be ".=hpux32" instead of ".=hpux64"
+
+ MULTILIB_OPTIONS = milp32/mlp64
+ MULTILIB_DIRNAMES = hpux32 hpux64
+ MULTILIB_MATCHES =
+ #MULTILIB_REDUNDANT_DIRS = .=hpux64
+ #MULTILIB_DONT_BUILD_DIRS =