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2.95 branch: ARM patches
- To: gcc-patches at gcc dot gnu dot org
- Subject: 2.95 branch: ARM patches
- From: Bernd Schmidt <bernds at redhat dot com>
- Date: Tue, 5 Dec 2000 19:14:55 +0000 (GMT)
I'll check in the following patches on the 2.95 branch; they are backports
from the mainline. They were requested by Jonathan Larmour and Richard
Earnshaw.
The Hint->HOST_WIDE_INT bits fix a build problem for cygwin toolchains.
The fix in arm_override_options makes sure the attributes in arm.md use
the right values.
The peephole changes prevent us from generating things like "move r0,(r0+)".
Tested by building an arm-elf toolchain and running the testsuite.
Bernd
2000-07-03 Nick Clifton <nickc@cygnus.com>
* config/arm/arm.md: Fix post increment and pre increment
peepholes so that they do not generate UNPREDICATBLE opcodes.
(ie ones where the increment clobbers the source/destination).
Mon Oct 25 00:42:35 1999 Jeffrey A Law (law@cygnus.com)
* arm.c (arm_override_options): Correct initialization of
arm_fast_multiply, arm_arch4, arm_arch5, arm_ld_sched,
arm_is_strong, and arm_is_6_or_7.
Thu Jul 29 19:01:58 1999 Bernd Schmidt <bernds@cygnus.co.uk>
* arm.h (Hint): Delete macro.
Substitute HOST_WIDE_INT for Hint in some prototypes.
* arm.c: Substitute HOST_WIDE_INT for Hint in one prototype.
Bernd
Index: arm.c
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/arm/arm.c,v
retrieving revision 1.43.4.5
diff -u -p -U8 -r1.43.4.5 arm.c
--- arm.c 1999/06/19 06:34:36 1.43.4.5
+++ arm.c 2000/12/05 19:07:16
@@ -63,17 +63,17 @@ static int broken_move PROTO ((rtx));
static char * fp_const_from_val PROTO ((REAL_VALUE_TYPE *));
static int eliminate_lr2ip PROTO ((rtx *));
static char * shift_op PROTO ((rtx, HOST_WIDE_INT *));
static int pattern_really_clobbers_lr PROTO ((rtx));
static int function_really_clobbers_lr PROTO ((rtx));
static void emit_multi_reg_push PROTO ((int));
static void emit_sfm PROTO ((int, int));
static enum arm_cond_code get_arm_condition_code PROTO ((rtx));
-static int const_ok_for_op RTX_CODE_PROTO ((Hint, Rcode));
+static int const_ok_for_op RTX_CODE_PROTO ((HOST_WIDE_INT, Rcode));
/* True if we are currently building a constant table. */
int making_const_table;
/* Define the information needed to generate branch insns. This is
stored from the compare operation. */
rtx arm_compare_op0, arm_compare_op1;
@@ -485,24 +485,24 @@ arm_override_options ()
which keeps r9 available. */
if (flag_pic && ! TARGET_APCS_STACK)
arm_pic_register = 10;
if (TARGET_APCS_FLOAT)
warning ("Passing floating point arguments in fp regs not yet supported");
/* Initialise boolean versions of the flags, for use in the arm.md file. */
- arm_fast_multiply = insn_flags & FL_FAST_MULT;
- arm_arch4 = insn_flags & FL_ARCH4;
+ arm_fast_multiply = (insn_flags & FL_FAST_MULT) != 0;
+ arm_arch4 = (insn_flags & FL_ARCH4) != 0;
- arm_ld_sched = tune_flags & FL_LDSCHED;
- arm_is_strong = tune_flags & FL_STRONG;
+ arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
+ arm_is_strong = (tune_flags & FL_STRONG) != 0;
arm_is_6_or_7 = ((tune_flags & (FL_MODE26 | FL_MODE32))
&& !(tune_flags & FL_ARCH4));
-
+
/* Default value for floating point code... if no co-processor
bus, then schedule for emulated floating point. Otherwise,
assume the user has an FPA.
Note: this does not prevent use of floating point instructions,
-msoft-float does that. */
arm_fpu = (tune_flags & FL_CO_PROC) ? FP_HARD : FP_SOFT3;
if (target_fp_name)
Index: arm.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/arm/arm.h,v
retrieving revision 1.34.4.3
diff -u -p -U8 -r1.34.4.3 arm.h
--- arm.h 1999/06/19 05:37:07 1.34.4.3
+++ arm.h 2000/12/05 19:07:17
@@ -2143,34 +2143,33 @@ struct rtx_def;
#define Rtx struct rtx_def *
#else
#define Rtx rtx
#endif
#ifndef HOST_WIDE_INT
#include "hwint.h"
#endif
-#define Hint HOST_WIDE_INT
#ifndef HAVE_MACHINE_MODES
#include "machmode.h"
#endif
#define Mmode enum machine_mode
#ifdef RTX_CODE
#define RTX_CODE_PROTO(ARGS) PROTO (ARGS)
#else
#define RTX_CODE_PROTO(ARGS) ()
#endif
#define Rcode enum rtx_code
void arm_override_options PROTO ((void));
int use_return_insn PROTO ((int));
-int const_ok_for_arm PROTO ((Hint));
-int arm_split_constant RTX_CODE_PROTO ((Rcode, Mmode, Hint, Rtx, Rtx, int));
+int const_ok_for_arm PROTO ((HOST_WIDE_INT));
+int arm_split_constant RTX_CODE_PROTO ((Rcode, Mmode, HOST_WIDE_INT, Rtx, Rtx, int));
Rcode arm_canonicalize_comparison RTX_CODE_PROTO ((Rcode, Rtx *));
int arm_return_in_memory PROTO ((Tree));
int legitimate_pic_operand_p PROTO ((Rtx));
Rtx legitimize_pic_address PROTO ((Rtx, Mmode, Rtx));
int is_pic PROTO ((Rtx));
void arm_finalize_pic PROTO ((void));
int arm_rtx_costs RTX_CODE_PROTO ((Rtx, Rcode));
int arm_adjust_cost PROTO ((Rtx, Rtx, Rtx, int));
@@ -2201,19 +2200,19 @@ int minmax_operator PROTO ((Rtx, Mmod
int cc_register PROTO ((Rtx, Mmode));
int dominant_cc_register PROTO ((Rtx, Mmode));
int symbol_mentioned_p PROTO ((Rtx));
int label_mentioned_p PROTO ((Rtx));
Rcode minmax_code PROTO ((Rtx));
int adjacent_mem_locations PROTO ((Rtx, Rtx));
int load_multiple_operation PROTO ((Rtx, Mmode));
int store_multiple_operation PROTO ((Rtx, Mmode));
-int load_multiple_sequence PROTO ((Rtx *, int, int *, int *, Hint *));
+int load_multiple_sequence PROTO ((Rtx *, int, int *, int *, HOST_WIDE_INT *));
char * emit_ldm_seq PROTO ((Rtx *, int));
-int store_multiple_sequence PROTO ((Rtx *, int, int *, int *, Hint *));
+int store_multiple_sequence PROTO ((Rtx *, int, int *, int *, HOST_WIDE_INT *));
char * emit_stm_seq PROTO ((Rtx *, int));
int arm_valid_machine_decl_attribute PROTO ((Tree, Tree, Tree));
Rtx arm_gen_load_multiple PROTO ((int, int, Rtx, int, int, int, int, int));
Rtx arm_gen_store_multiple PROTO ((int, int, Rtx, int, int, int, int, int));
int arm_gen_movstrqi PROTO ((Rtx *));
Rtx gen_rotated_half_load PROTO ((Rtx));
Mmode arm_select_cc_mode RTX_CODE_PROTO ((Rcode, Rtx, Rtx));
Rtx gen_compare_reg RTX_CODE_PROTO ((Rcode, Rtx, Rtx, int));
Index: arm.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/arm/arm.md,v
retrieving revision 1.27.4.3
diff -u -p -U8 -r1.27.4.3 arm.md
--- arm.md 2000/05/26 09:31:50 1.27.4.3
+++ arm.md 2000/12/05 19:07:18
@@ -5793,84 +5793,88 @@
"ldr%?\\t%5, [%0, -%3%S2]!\\t%@ loadhi"
[(set_attr "type" "load")])
; It can also support extended post-inc expressions, but combine doesn't
; try these....
; It doesn't seem worth adding peepholes for anything but the most common
; cases since, unlike combine, the increment must immediately follow the load
; for this pattern to match.
-; When loading we must watch to see that the base register isn't trampled by
-; the load. In such cases this isn't a post-inc expression.
+; We must watch to see that the source/destination register isn't also the
+; same as the base address register, and that if the index is a register,
+; that it is not the same as the base address register. In such cases the
+; instruction that we would generate would have UNPREDICTABLE behaviour so
+; we cannot use it.
(define_peephole
[(set (mem:QI (match_operand:SI 0 "s_register_operand" "+r"))
(match_operand:QI 2 "s_register_operand" "r"))
(set (match_dup 0)
(plus:SI (match_dup 0) (match_operand:SI 1 "index_operand" "rJ")))]
- ""
+ "(REGNO (operands[2]) != REGNO (operands[0]))
+ && (GET_CODE (operands[1]) != REG || (REGNO (operands[1]) != REGNO (operands[0])))"
"str%?b\\t%2, [%0], %1")
(define_peephole
[(set (match_operand:QI 0 "s_register_operand" "=r")
(mem:QI (match_operand:SI 1 "s_register_operand" "+r")))
(set (match_dup 1)
(plus:SI (match_dup 1) (match_operand:SI 2 "index_operand" "rJ")))]
- "REGNO(operands[0]) != REGNO(operands[1])
- && (GET_CODE (operands[2]) != REG
- || REGNO(operands[0]) != REGNO (operands[2]))"
+ "REGNO (operands[0]) != REGNO (operands[1])
+ && (GET_CODE (operands[2]) != REG || REGNO (operands[0]) != REGNO (operands[2]))"
"ldr%?b\\t%0, [%1], %2")
(define_peephole
[(set (mem:SI (match_operand:SI 0 "s_register_operand" "+r"))
(match_operand:SI 2 "s_register_operand" "r"))
(set (match_dup 0)
(plus:SI (match_dup 0) (match_operand:SI 1 "index_operand" "rJ")))]
- ""
+ "(REGNO (operands[2]) != REGNO (operands[0]))
+ && (GET_CODE (operands[1]) != REG || (REGNO (operands[1]) != REGNO (operands[0])))"
"str%?\\t%2, [%0], %1")
(define_peephole
[(set (match_operand:HI 0 "s_register_operand" "=r")
(mem:HI (match_operand:SI 1 "s_register_operand" "+r")))
(set (match_dup 1)
(plus:SI (match_dup 1) (match_operand:SI 2 "index_operand" "rJ")))]
"(! BYTES_BIG_ENDIAN)
&& ! TARGET_SHORT_BY_BYTES
- && REGNO(operands[0]) != REGNO(operands[1])
- && (GET_CODE (operands[2]) != REG
- || REGNO(operands[0]) != REGNO (operands[2]))"
+ && REGNO (operands[0]) != REGNO (operands[1])
+ && (GET_CODE (operands[2]) != REG || REGNO (operands[0]) != REGNO (operands[2]))"
"ldr%?\\t%0, [%1], %2\\t%@ loadhi")
(define_peephole
[(set (match_operand:SI 0 "s_register_operand" "=r")
(mem:SI (match_operand:SI 1 "s_register_operand" "+r")))
(set (match_dup 1)
(plus:SI (match_dup 1) (match_operand:SI 2 "index_operand" "rJ")))]
- "REGNO(operands[0]) != REGNO(operands[1])
- && (GET_CODE (operands[2]) != REG
- || REGNO(operands[0]) != REGNO (operands[2]))"
+ "REGNO (operands[0]) != REGNO (operands[1])
+ && (GET_CODE (operands[2]) != REG || REGNO (operands[0]) != REGNO (operands[2]))"
"ldr%?\\t%0, [%1], %2")
(define_peephole
[(set (mem:QI (plus:SI (match_operand:SI 0 "s_register_operand" "+r")
(match_operand:SI 1 "index_operand" "rJ")))
(match_operand:QI 2 "s_register_operand" "r"))
(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))]
- ""
+ "(REGNO (operands[2]) != REGNO (operands[0]))
+ && (GET_CODE (operands[1]) != REG || (REGNO (operands[1]) != REGNO (operands[0])))"
"str%?b\\t%2, [%0, %1]!")
(define_peephole
[(set (mem:QI (plus:SI (match_operator:SI 4 "shift_operator"
[(match_operand:SI 0 "s_register_operand" "r")
(match_operand:SI 1 "const_int_operand" "n")])
(match_operand:SI 2 "s_register_operand" "+r")))
(match_operand:QI 3 "s_register_operand" "r"))
(set (match_dup 2) (plus:SI (match_op_dup 4 [(match_dup 0) (match_dup 1)])
(match_dup 2)))]
- ""
+ "REGNO (operands[0]) != REGNO (operands[2])
+ && REGNO (operands[3]) != REGNO (operands[2])"
"str%?b\\t%3, [%2, %0%S4]!")
; This pattern is never tried by combine, so do it as a peephole
(define_peephole
[(set (match_operand:SI 0 "s_register_operand" "=r")
(match_operand:SI 1 "s_register_operand" "r"))
(set (reg:CC 24)