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Minor PA fixes
- To: gcc-patches at gcc dot gnu dot org
- Subject: Minor PA fixes
- From: Jeffrey A Law <law at redhat dot com>
- Date: Thu, 30 Nov 2000 01:15:59 -0700
- Reply-To: law at redhat dot com
The new checks to avoid holes in the operand arrays for patterns exposed
a couple buglets in the PA backend.
* pa.md (conditional moves): Avoid holes in operand list.
(mod, umod patterns): Similarly.
(variable extract/shift patterns): Similarly.
Index: pa.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/pa/pa.md,v
retrieving revision 1.72
diff -c -3 -p -r1.72 pa.md
*** pa.md 2000/11/30 06:37:34 1.72
--- pa.md 2000/11/30 08:05:52
***************
*** 1098,1114 ****
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
(if_then_else:SI
! (match_operator 5 "comparison_operator"
[(match_operand:SI 3 "register_operand" "r,r,r,r")
(match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI")])
(match_operand:SI 1 "reg_or_cint_move_operand" "0,J,N,K")
(const_int 0)))]
""
"@
! {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldi 0,%0
! {com%I4clr|cmp%I4clr},%B5 %4,%3,%0\;ldi %1,%0
! {com%I4clr|cmp%I4clr},%B5 %4,%3,%0\;ldil L'%1,%0
! {com%I4clr|cmp%I4clr},%B5 %4,%3,%0\;{zdepi|depwi,z} %Z1,%0"
[(set_attr "type" "multi,multi,multi,nullshift")
(set_attr "length" "8,8,8,8")])
--- 1098,1114 ----
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
(if_then_else:SI
! (match_operator 2 "comparison_operator"
[(match_operand:SI 3 "register_operand" "r,r,r,r")
(match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI")])
(match_operand:SI 1 "reg_or_cint_move_operand" "0,J,N,K")
(const_int 0)))]
""
"@
! {com%I4clr|cmp%I4clr},%S2 %4,%3,%%r0\;ldi 0,%0
! {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldi %1,%0
! {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldil L'%1,%0
! {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;{zdepi|depwi,z} %Z1,%0"
[(set_attr "type" "multi,multi,multi,nullshift")
(set_attr "length" "8,8,8,8")])
***************
*** 1165,1182 ****
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r")
(if_then_else:DI
! (match_operator 5 "comparison_operator"
[(match_operand:DI 3 "register_operand" "r,r,r,r,r")
(match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI")])
(match_operand:DI 1 "reg_or_cint_move_operand" "0,r,J,N,K")
(const_int 0)))]
"TARGET_64BIT"
"@
! cmp%I4clr,*%S5 %4,%3,%%r0\;ldi 0,%0
! cmp%I4clr,*%B5 %4,%3,%0\;copy %1,%0
! cmp%I4clr,*%B5 %4,%3,%0\;ldi %1,%0
! cmp%I4clr,*%B5 %4,%3,%0\;ldil L'%1,%0
! cmp%I4clr,*%B5 %4,%3,%0\;depdi,z %z1,%0"
[(set_attr "type" "multi,multi,multi,multi,nullshift")
(set_attr "length" "8,8,8,8,8")])
--- 1165,1182 ----
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r")
(if_then_else:DI
! (match_operator 2 "comparison_operator"
[(match_operand:DI 3 "register_operand" "r,r,r,r,r")
(match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI")])
(match_operand:DI 1 "reg_or_cint_move_operand" "0,r,J,N,K")
(const_int 0)))]
"TARGET_64BIT"
"@
! cmp%I4clr,*%S2 %4,%3,%%r0\;ldi 0,%0
! cmp%I4clr,*%B2 %4,%3,%0\;copy %1,%0
! cmp%I4clr,*%B2 %4,%3,%0\;ldi %1,%0
! cmp%I4clr,*%B2 %4,%3,%0\;ldil L'%1,%0
! cmp%I4clr,*%B2 %4,%3,%0\;depdi,z %z1,%0"
[(set_attr "type" "multi,multi,multi,multi,nullshift")
(set_attr "length" "8,8,8,8,8")])
***************
*** 4068,4074 ****
(define_insn ""
[(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
(clobber (match_operand:SI 0 "register_operand" "=a"))
! (clobber (match_operand:SI 2 "register_operand" "=&r"))
(clobber (reg:SI 26))
(clobber (reg:SI 25))
(clobber (reg:SI 31))]
--- 4104,4110 ----
(define_insn ""
[(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
(clobber (match_operand:SI 0 "register_operand" "=a"))
! (clobber (match_operand:SI 1 "register_operand" "=&r"))
(clobber (reg:SI 26))
(clobber (reg:SI 25))
(clobber (reg:SI 31))]
***************
*** 4123,4129 ****
(define_insn ""
[(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
(clobber (match_operand:SI 0 "register_operand" "=a"))
! (clobber (match_operand:SI 2 "register_operand" "=&r"))
(clobber (reg:SI 26))
(clobber (reg:SI 25))
(clobber (reg:SI 31))]
--- 4159,4165 ----
(define_insn ""
[(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
(clobber (match_operand:SI 0 "register_operand" "=a"))
! (clobber (match_operand:SI 1 "register_operand" "=&r"))
(clobber (reg:SI 26))
(clobber (reg:SI 25))
(clobber (reg:SI 31))]
***************
*** 6210,6216 ****
[(set (match_operand:SI 0 "register_operand" "=r")
(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
(const_int 1)
! (match_operand:SI 3 "register_operand" "q")))]
""
"{vextru %1,1,%0|extrw,u %1,%%sar,1,%0}"
[(set_attr "type" "shift")
--- 6246,6252 ----
[(set (match_operand:SI 0 "register_operand" "=r")
(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
(const_int 1)
! (match_operand:SI 2 "register_operand" "q")))]
""
"{vextru %1,1,%0|extrw,u %1,%%sar,1,%0}"
[(set_attr "type" "shift")
***************
*** 6230,6236 ****
[(set (match_operand:DI 0 "register_operand" "=r")
(zero_extract:DI (match_operand:DI 1 "register_operand" "r")
(const_int 1)
! (match_operand:DI 3 "register_operand" "q")))]
"TARGET_64BIT"
"extrd,u %1,%%sar,1,%0"
[(set_attr "type" "shift")
--- 6266,6272 ----
[(set (match_operand:DI 0 "register_operand" "=r")
(zero_extract:DI (match_operand:DI 1 "register_operand" "r")
(const_int 1)
! (match_operand:DI 2 "register_operand" "q")))]
"TARGET_64BIT"
"extrd,u %1,%%sar,1,%0"
[(set_attr "type" "shift")
***************
*** 6267,6273 ****
[(set (match_operand:SI 0 "register_operand" "=r")
(sign_extract:SI (match_operand:SI 1 "register_operand" "r")
(const_int 1)
! (match_operand:SI 3 "register_operand" "q")))]
"!TARGET_64BIT"
"{vextrs %1,1,%0|extrw,s %1,%%sar,1,%0}"
[(set_attr "type" "shift")
--- 6303,6309 ----
[(set (match_operand:SI 0 "register_operand" "=r")
(sign_extract:SI (match_operand:SI 1 "register_operand" "r")
(const_int 1)
! (match_operand:SI 2 "register_operand" "q")))]
"!TARGET_64BIT"
"{vextrs %1,1,%0|extrw,s %1,%%sar,1,%0}"
[(set_attr "type" "shift")
***************
*** 6287,6293 ****
[(set (match_operand:DI 0 "register_operand" "=r")
(sign_extract:DI (match_operand:DI 1 "register_operand" "r")
(const_int 1)
! (match_operand:DI 3 "register_operand" "q")))]
"TARGET_64BIT"
"extrd,s %1,%%sar,1,%0"
[(set_attr "type" "shift")
--- 6323,6329 ----
[(set (match_operand:DI 0 "register_operand" "=r")
(sign_extract:DI (match_operand:DI 1 "register_operand" "r")
(const_int 1)
! (match_operand:DI 2 "register_operand" "q")))]
"TARGET_64BIT"
"extrd,s %1,%%sar,1,%0"
[(set_attr "type" "shift")