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Use new Constant Definitions feature in arm.md
- To: gcc-patches at gcc dot gnu dot org
- Subject: Use new Constant Definitions feature in arm.md
- From: Nick Clifton <nickc at redhat dot com>
- Date: Wed, 22 Nov 2000 12:46:11 -0800
Hi Guys,
I am checking in the patch below to make use of the new constant
definitions feature for md files. It replaces the register numbers
14, 15 and 24 with their symbolic names.
Cheers
Nick
2000-11-22 Nick Clifton <nickc@redhat.com>
* config/arm/arm.md (define_constants): Define symbolic names for
the link register, last integer register and the fake CC register.
Update patterns to use these symbolic names.
Index: config/arm/arm.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/arm/arm.md,v
retrieving revision 1.64
diff -p -r1.64 arm.md
*** arm.md 2000/11/13 13:58:51 1.64
--- arm.md 2000/11/22 20:43:40
***************
*** 328,334 ****
--- 328,343 ----
(eq_attr "type" "!mult,load,store1,store2,store3,store4")) 32 32)
;;---------------------------------------------------------------------------
+ ;; Make code more maintainable by using names for fixed registers.
+ (define_constants
+ [(LR_REGNUM 14)
+ (LAST_ARM_REGNUM 15)
+ (CC_REGNUM 24)]
+ )
+
+ ;;---------------------------------------------------------------------------
+
;; Note: For DImode insns, there is normally no reason why operands should
;; not be in the same register, what we don't want is for something being
;; written to partially overlap something that is an input.
***************
*** 339,352 ****
[(set (match_operand:DI 0 "s_register_operand" "")
(plus:DI (match_operand:DI 1 "s_register_operand" "")
(match_operand:DI 2 "s_register_operand" "")))
! (clobber (reg:CC 24))]
"TARGET_ARM && reload_completed
"
! [(parallel [(set (reg:CC_C 24)
(compare:CC_C (plus:SI (match_dup 1) (match_dup 2))
(match_dup 1)))
(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
! (set (match_dup 3) (plus:SI (ltu:SI (reg:CC_C 24) (const_int 0))
(plus:SI (match_dup 4) (match_dup 5))))]
"
{
--- 348,361 ----
[(set (match_operand:DI 0 "s_register_operand" "")
(plus:DI (match_operand:DI 1 "s_register_operand" "")
(match_operand:DI 2 "s_register_operand" "")))
! (clobber (reg:CC CC_REGNUM))]
"TARGET_ARM && reload_completed
"
! [(parallel [(set (reg:CC_C CC_REGNUM)
(compare:CC_C (plus:SI (match_dup 1) (match_dup 2))
(match_dup 1)))
(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
! (set (match_dup 3) (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))
(plus:SI (match_dup 4) (match_dup 5))))]
"
{
***************
*** 367,380 ****
[(set (match_operand:DI 0 "s_register_operand" "")
(plus:DI (sign_extend:DI (match_operand:SI 2 "s_register_operand" ""))
(match_operand:DI 1 "s_register_operand" "")))
! (clobber (reg:CC 24))]
"TARGET_ARM && reload_completed
"
! [(parallel [(set (reg:CC_C 24)
(compare:CC_C (plus:SI (match_dup 1) (match_dup 2))
(match_dup 1)))
(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
! (set (match_dup 3) (plus:SI (ltu:SI (reg:CC_C 24) (const_int 0))
(plus:SI (ashiftrt:SI (match_dup 2)
(const_int 31))
(match_dup 4))))]
--- 376,389 ----
[(set (match_operand:DI 0 "s_register_operand" "")
(plus:DI (sign_extend:DI (match_operand:SI 2 "s_register_operand" ""))
(match_operand:DI 1 "s_register_operand" "")))
! (clobber (reg:CC CC_REGNUM))]
"TARGET_ARM && reload_completed
"
! [(parallel [(set (reg:CC_C CC_REGNUM)
(compare:CC_C (plus:SI (match_dup 1) (match_dup 2))
(match_dup 1)))
(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
! (set (match_dup 3) (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))
(plus:SI (ashiftrt:SI (match_dup 2)
(const_int 31))
(match_dup 4))))]
***************
*** 396,409 ****
[(set (match_operand:DI 0 "s_register_operand" "")
(plus:DI (zero_extend:DI (match_operand:SI 2 "s_register_operand" ""))
(match_operand:DI 1 "s_register_operand" "")))
! (clobber (reg:CC 24))]
"TARGET_ARM && reload_completed
"
! [(parallel [(set (reg:CC_C 24)
(compare:CC_C (plus:SI (match_dup 1) (match_dup 2))
(match_dup 1)))
(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
! (set (match_dup 3) (plus:SI (ltu:SI (reg:CC_C 24) (const_int 0))
(plus:SI (match_dup 4) (const_int 0))))]
"
{
--- 405,418 ----
[(set (match_operand:DI 0 "s_register_operand" "")
(plus:DI (zero_extend:DI (match_operand:SI 2 "s_register_operand" ""))
(match_operand:DI 1 "s_register_operand" "")))
! (clobber (reg:CC CC_REGNUM))]
"TARGET_ARM && reload_completed
"
! [(parallel [(set (reg:CC_C CC_REGNUM)
(compare:CC_C (plus:SI (match_dup 1) (match_dup 2))
(match_dup 1)))
(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
! (set (match_dup 3) (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))
(plus:SI (match_dup 4) (const_int 0))))]
"
{
***************
*** 422,428 ****
[(set (match_operand:DI 0 "s_register_operand" "")
(plus:DI (match_operand:DI 1 "s_register_operand" "")
(match_operand:DI 2 "s_register_operand" "")))
! (clobber (reg:CC 24))])]
"TARGET_EITHER"
"
if (TARGET_THUMB)
--- 431,437 ----
[(set (match_operand:DI 0 "s_register_operand" "")
(plus:DI (match_operand:DI 1 "s_register_operand" "")
(match_operand:DI 2 "s_register_operand" "")))
! (clobber (reg:CC CC_REGNUM))])]
"TARGET_EITHER"
"
if (TARGET_THUMB)
***************
*** 439,445 ****
[(set (match_operand:DI 0 "register_operand" "=l")
(plus:DI (match_operand:DI 1 "register_operand" "%0")
(match_operand:DI 2 "register_operand" "l")))
! (clobber (reg:CC 24))
]
"TARGET_THUMB"
"add\\t%Q0, %Q0, %Q2\;adc\\t%R0, %R0, %R2"
--- 448,454 ----
[(set (match_operand:DI 0 "register_operand" "=l")
(plus:DI (match_operand:DI 1 "register_operand" "%0")
(match_operand:DI 2 "register_operand" "l")))
! (clobber (reg:CC CC_REGNUM))
]
"TARGET_THUMB"
"add\\t%Q0, %Q0, %Q2\;adc\\t%R0, %R0, %R2"
***************
*** 450,456 ****
[(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
(plus:DI (match_operand:DI 1 "s_register_operand" "%0, 0")
(match_operand:DI 2 "s_register_operand" "r, 0")))
! (clobber (reg:CC 24))]
"TARGET_ARM
"
"#"
--- 459,465 ----
[(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
(plus:DI (match_operand:DI 1 "s_register_operand" "%0, 0")
(match_operand:DI 2 "s_register_operand" "r, 0")))
! (clobber (reg:CC CC_REGNUM))]
"TARGET_ARM
"
"#"
***************
*** 463,469 ****
(plus:DI (sign_extend:DI
(match_operand:SI 2 "s_register_operand" "r,r"))
(match_operand:DI 1 "s_register_operand" "r,0")))
! (clobber (reg:CC 24))]
"TARGET_ARM
"
"#"
--- 472,478 ----
(plus:DI (sign_extend:DI
(match_operand:SI 2 "s_register_operand" "r,r"))
(match_operand:DI 1 "s_register_operand" "r,0")))
! (clobber (reg:CC CC_REGNUM))]
"TARGET_ARM
"
"#"
***************
*** 476,482 ****
(plus:DI (zero_extend:DI
(match_operand:SI 2 "s_register_operand" "r,r"))
(match_operand:DI 1 "s_register_operand" "r,0")))
! (clobber (reg:CC 24))
]
"TARGET_ARM
"
--- 485,491 ----
(plus:DI (zero_extend:DI
(match_operand:SI 2 "s_register_operand" "r,r"))
(match_operand:DI 1 "s_register_operand" "r,0")))
! (clobber (reg:CC CC_REGNUM))
]
"TARGET_ARM
"
***************
*** 573,579 ****
)
(define_insn "*addsi3_compare0"
! [(set (reg:CC_NOOV 24)
(compare:CC_NOOV
(plus:SI (match_operand:SI 1 "s_register_operand" "r, r")
(match_operand:SI 2 "arm_add_operand" "rI,L"))
--- 582,588 ----
)
(define_insn "*addsi3_compare0"
! [(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV
(plus:SI (match_operand:SI 1 "s_register_operand" "r, r")
(match_operand:SI 2 "arm_add_operand" "rI,L"))
***************
*** 588,594 ****
)
(define_insn "*addsi3_compare0_scratch"
! [(set (reg:CC_NOOV 24)
(compare:CC_NOOV
(plus:SI (match_operand:SI 0 "s_register_operand" "r, r")
(match_operand:SI 1 "arm_add_operand" "rI,L"))
--- 597,603 ----
)
(define_insn "*addsi3_compare0_scratch"
! [(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV
(plus:SI (match_operand:SI 0 "s_register_operand" "r, r")
(match_operand:SI 1 "arm_add_operand" "rI,L"))
***************
*** 604,610 ****
;; patterns, except we write them slightly different - the combiner
;; tends to generate them this way.
(define_insn "*addsi3_compare0_for_combiner"
! [(set (reg:CC 24)
(compare:CC
(match_operand:SI 1 "s_register_operand" "r,r")
(neg:SI (match_operand:SI 2 "arm_add_operand" "rI,L"))))
--- 613,619 ----
;; patterns, except we write them slightly different - the combiner
;; tends to generate them this way.
(define_insn "*addsi3_compare0_for_combiner"
! [(set (reg:CC CC_REGNUM)
(compare:CC
(match_operand:SI 1 "s_register_operand" "r,r")
(neg:SI (match_operand:SI 2 "arm_add_operand" "rI,L"))))
***************
*** 618,624 ****
)
(define_insn "*addsi3_compare0_scratch_for_combiner"
! [(set (reg:CC 24)
(compare:CC
(match_operand:SI 0 "s_register_operand" "r,r")
(neg:SI (match_operand:SI 1 "arm_add_operand" "rI,L"))))]
--- 627,633 ----
)
(define_insn "*addsi3_compare0_scratch_for_combiner"
! [(set (reg:CC CC_REGNUM)
(compare:CC
(match_operand:SI 0 "s_register_operand" "r,r")
(neg:SI (match_operand:SI 1 "arm_add_operand" "rI,L"))))]
***************
*** 634,640 ****
;; either GEU or LTU, so we can use the carry flag from the addition
;; instead of doing the compare a second time.
(define_insn "*addsi3_compare_op1"
! [(set (reg:CC_C 24)
(compare:CC_C
(plus:SI (match_operand:SI 1 "s_register_operand" "r,r")
(match_operand:SI 2 "arm_add_operand" "rI,L"))
--- 643,649 ----
;; either GEU or LTU, so we can use the carry flag from the addition
;; instead of doing the compare a second time.
(define_insn "*addsi3_compare_op1"
! [(set (reg:CC_C CC_REGNUM)
(compare:CC_C
(plus:SI (match_operand:SI 1 "s_register_operand" "r,r")
(match_operand:SI 2 "arm_add_operand" "rI,L"))
***************
*** 649,655 ****
)
(define_insn "*addsi3_compare_op2"
! [(set (reg:CC_C 24)
(compare:CC_C
(plus:SI (match_operand:SI 1 "s_register_operand" "r,r")
(match_operand:SI 2 "arm_add_operand" "rI,L"))
--- 658,664 ----
)
(define_insn "*addsi3_compare_op2"
! [(set (reg:CC_C CC_REGNUM)
(compare:CC_C
(plus:SI (match_operand:SI 1 "s_register_operand" "r,r")
(match_operand:SI 2 "arm_add_operand" "rI,L"))
***************
*** 664,670 ****
)
(define_insn "*compare_addsi2_op0"
! [(set (reg:CC_C 24)
(compare:CC_C
(plus:SI (match_operand:SI 0 "s_register_operand" "r,r")
(match_operand:SI 1 "arm_add_operand" "rI,L"))
--- 673,679 ----
)
(define_insn "*compare_addsi2_op0"
! [(set (reg:CC_C CC_REGNUM)
(compare:CC_C
(plus:SI (match_operand:SI 0 "s_register_operand" "r,r")
(match_operand:SI 1 "arm_add_operand" "rI,L"))
***************
*** 677,683 ****
)
(define_insn "*compare_addsi2_op1"
! [(set (reg:CC_C 24)
(compare:CC_C
(plus:SI (match_operand:SI 0 "s_register_operand" "r,r")
(match_operand:SI 1 "arm_add_operand" "rI,L"))
--- 686,692 ----
)
(define_insn "*compare_addsi2_op1"
! [(set (reg:CC_C CC_REGNUM)
(compare:CC_C
(plus:SI (match_operand:SI 0 "s_register_operand" "r,r")
(match_operand:SI 1 "arm_add_operand" "rI,L"))
***************
*** 691,697 ****
(define_insn "*addsi3_carryin"
[(set (match_operand:SI 0 "s_register_operand" "=r")
! (plus:SI (ltu:SI (reg:CC_C 24) (const_int 0))
(plus:SI (match_operand:SI 1 "s_register_operand" "r")
(match_operand:SI 2 "arm_rhs_operand" "rI"))))]
"TARGET_ARM"
--- 700,706 ----
(define_insn "*addsi3_carryin"
[(set (match_operand:SI 0 "s_register_operand" "=r")
! (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))
(plus:SI (match_operand:SI 1 "s_register_operand" "r")
(match_operand:SI 2 "arm_rhs_operand" "rI"))))]
"TARGET_ARM"
***************
*** 701,707 ****
(define_insn "*addsi3_carryin_shift"
[(set (match_operand:SI 0 "s_register_operand" "")
! (plus:SI (ltu:SI (reg:CC_C 24) (const_int 0))
(plus:SI
(match_operator:SI 2 "shift_operator"
[(match_operand:SI 3 "s_register_operand" "")
--- 710,716 ----
(define_insn "*addsi3_carryin_shift"
[(set (match_operand:SI 0 "s_register_operand" "")
! (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))
(plus:SI
(match_operator:SI 2 "shift_operator"
[(match_operand:SI 3 "s_register_operand" "")
***************
*** 716,722 ****
[(set (match_operand:SI 0 "s_register_operand" "=r")
(plus:SI (plus:SI (match_operand:SI 1 "s_register_operand" "r")
(match_operand:SI 2 "arm_rhs_operand" "rI"))
! (ltu:SI (reg:CC_C 24) (const_int 0))))]
"TARGET_ARM"
"adc%?\\t%0, %1, %2"
[(set_attr "conds" "use")]
--- 725,731 ----
[(set (match_operand:SI 0 "s_register_operand" "=r")
(plus:SI (plus:SI (match_operand:SI 1 "s_register_operand" "r")
(match_operand:SI 2 "arm_rhs_operand" "rI"))
! (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
"TARGET_ARM"
"adc%?\\t%0, %1, %2"
[(set_attr "conds" "use")]
***************
*** 724,730 ****
(define_insn "*addsi3_carryin_alt2"
[(set (match_operand:SI 0 "s_register_operand" "=r")
! (plus:SI (plus:SI (ltu:SI (reg:CC_C 24) (const_int 0))
(match_operand:SI 1 "s_register_operand" "r"))
(match_operand:SI 2 "arm_rhs_operand" "rI")))]
"TARGET_ARM"
--- 733,739 ----
(define_insn "*addsi3_carryin_alt2"
[(set (match_operand:SI 0 "s_register_operand" "=r")
! (plus:SI (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))
(match_operand:SI 1 "s_register_operand" "r"))
(match_operand:SI 2 "arm_rhs_operand" "rI")))]
"TARGET_ARM"
***************
*** 734,740 ****
(define_insn "*addsi3_carryin_alt3"
[(set (match_operand:SI 0 "s_register_operand" "=r")
! (plus:SI (plus:SI (ltu:SI (reg:CC_C 24) (const_int 0))
(match_operand:SI 2 "arm_rhs_operand" "rI"))
(match_operand:SI 1 "s_register_operand" "r")))]
"TARGET_ARM"
--- 743,749 ----
(define_insn "*addsi3_carryin_alt3"
[(set (match_operand:SI 0 "s_register_operand" "=r")
! (plus:SI (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))
(match_operand:SI 2 "arm_rhs_operand" "rI"))
(match_operand:SI 1 "s_register_operand" "r")))]
"TARGET_ARM"
***************
*** 896,902 ****
[(set (match_operand:DI 0 "s_register_operand" "")
(minus:DI (match_operand:DI 1 "s_register_operand" "")
(match_operand:DI 2 "s_register_operand" "")))
! (clobber (reg:CC 24))])]
"TARGET_EITHER"
"
if (TARGET_THUMB)
--- 905,911 ----
[(set (match_operand:DI 0 "s_register_operand" "")
(minus:DI (match_operand:DI 1 "s_register_operand" "")
(match_operand:DI 2 "s_register_operand" "")))
! (clobber (reg:CC CC_REGNUM))])]
"TARGET_EITHER"
"
if (TARGET_THUMB)
***************
*** 913,919 ****
[(set (match_operand:DI 0 "s_register_operand" "=&r,&r,&r")
(minus:DI (match_operand:DI 1 "s_register_operand" "0,r,0")
(match_operand:DI 2 "s_register_operand" "r,0,0")))
! (clobber (reg:CC 24))]
"TARGET_ARM"
"subs\\t%Q0, %Q1, %Q2\;sbc\\t%R0, %R1, %R2"
[(set_attr "conds" "clob")
--- 922,928 ----
[(set (match_operand:DI 0 "s_register_operand" "=&r,&r,&r")
(minus:DI (match_operand:DI 1 "s_register_operand" "0,r,0")
(match_operand:DI 2 "s_register_operand" "r,0,0")))
! (clobber (reg:CC CC_REGNUM))]
"TARGET_ARM"
"subs\\t%Q0, %Q1, %Q2\;sbc\\t%R0, %R1, %R2"
[(set_attr "conds" "clob")
***************
*** 924,930 ****
[(set (match_operand:DI 0 "register_operand" "=l")
(minus:DI (match_operand:DI 1 "register_operand" "0")
(match_operand:DI 2 "register_operand" "l")))
! (clobber (reg:CC 24))]
"TARGET_THUMB"
"sub\\t%Q0, %Q0, %Q2\;sbc\\t%R0, %R0, %R2"
[(set_attr "length" "4")]
--- 933,939 ----
[(set (match_operand:DI 0 "register_operand" "=l")
(minus:DI (match_operand:DI 1 "register_operand" "0")
(match_operand:DI 2 "register_operand" "l")))
! (clobber (reg:CC CC_REGNUM))]
"TARGET_THUMB"
"sub\\t%Q0, %Q0, %Q2\;sbc\\t%R0, %R0, %R2"
[(set_attr "length" "4")]
***************
*** 935,941 ****
(minus:DI (match_operand:DI 1 "s_register_operand" "?r,0")
(zero_extend:DI
(match_operand:SI 2 "s_register_operand" "r,r"))))
! (clobber (reg:CC 24))]
"TARGET_ARM"
"subs\\t%Q0, %Q1, %2\;sbc\\t%R0, %R1, #0"
[(set_attr "conds" "clob")
--- 944,950 ----
(minus:DI (match_operand:DI 1 "s_register_operand" "?r,0")
(zero_extend:DI
(match_operand:SI 2 "s_register_operand" "r,r"))))
! (clobber (reg:CC CC_REGNUM))]
"TARGET_ARM"
"subs\\t%Q0, %Q1, %2\;sbc\\t%R0, %R1, #0"
[(set_attr "conds" "clob")
***************
*** 947,953 ****
(minus:DI (match_operand:DI 1 "s_register_operand" "r,0")
(sign_extend:DI
(match_operand:SI 2 "s_register_operand" "r,r"))))
! (clobber (reg:CC 24))]
"TARGET_ARM"
"subs\\t%Q0, %Q1, %2\;sbc\\t%R0, %R1, %2, asr #31"
[(set_attr "conds" "clob")
--- 956,962 ----
(minus:DI (match_operand:DI 1 "s_register_operand" "r,0")
(sign_extend:DI
(match_operand:SI 2 "s_register_operand" "r,r"))))
! (clobber (reg:CC CC_REGNUM))]
"TARGET_ARM"
"subs\\t%Q0, %Q1, %2\;sbc\\t%R0, %R1, %2, asr #31"
[(set_attr "conds" "clob")
***************
*** 959,965 ****
(minus:DI (zero_extend:DI
(match_operand:SI 2 "s_register_operand" "r,r"))
(match_operand:DI 1 "s_register_operand" "?r,0")))
! (clobber (reg:CC 24))]
"TARGET_ARM"
"rsbs\\t%Q0, %Q1, %2\;rsc\\t%R0, %R1, #0"
[(set_attr "conds" "clob")
--- 968,974 ----
(minus:DI (zero_extend:DI
(match_operand:SI 2 "s_register_operand" "r,r"))
(match_operand:DI 1 "s_register_operand" "?r,0")))
! (clobber (reg:CC CC_REGNUM))]
"TARGET_ARM"
"rsbs\\t%Q0, %Q1, %2\;rsc\\t%R0, %R1, #0"
[(set_attr "conds" "clob")
***************
*** 971,977 ****
(minus:DI (sign_extend:DI
(match_operand:SI 2 "s_register_operand" "r,r"))
(match_operand:DI 1 "s_register_operand" "?r,0")))
! (clobber (reg:CC 24))]
"TARGET_ARM"
"rsbs\\t%Q0, %Q1, %2\;rsc\\t%R0, %R1, %2, asr #31"
[(set_attr "conds" "clob")
--- 980,986 ----
(minus:DI (sign_extend:DI
(match_operand:SI 2 "s_register_operand" "r,r"))
(match_operand:DI 1 "s_register_operand" "?r,0")))
! (clobber (reg:CC CC_REGNUM))]
"TARGET_ARM"
"rsbs\\t%Q0, %Q1, %2\;rsc\\t%R0, %R1, %2, asr #31"
[(set_attr "conds" "clob")
***************
*** 984,990 ****
(match_operand:SI 1 "s_register_operand" "r"))
(zero_extend:DI
(match_operand:SI 2 "s_register_operand" "r"))))
! (clobber (reg:CC 24))]
"TARGET_ARM"
"subs\\t%Q0, %1, %2\;rsc\\t%R0, %1, %1"
[(set_attr "conds" "clob")
--- 993,999 ----
(match_operand:SI 1 "s_register_operand" "r"))
(zero_extend:DI
(match_operand:SI 2 "s_register_operand" "r"))))
! (clobber (reg:CC CC_REGNUM))]
"TARGET_ARM"
"subs\\t%Q0, %1, %2\;rsc\\t%R0, %1, %1"
[(set_attr "conds" "clob")
***************
*** 1048,1054 ****
)
(define_insn "*subsi3_compare0"
! [(set (reg:CC_NOOV 24)
(compare:CC_NOOV
(minus:SI (match_operand:SI 1 "arm_rhs_operand" "r,I")
(match_operand:SI 2 "arm_rhs_operand" "rI,r"))
--- 1057,1063 ----
)
(define_insn "*subsi3_compare0"
! [(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV
(minus:SI (match_operand:SI 1 "arm_rhs_operand" "r,I")
(match_operand:SI 2 "arm_rhs_operand" "rI,r"))
***************
*** 1188,1194 ****
)
(define_insn "*mulsi3_compare0"
! [(set (reg:CC_NOOV 24)
(compare:CC_NOOV (mult:SI
(match_operand:SI 2 "s_register_operand" "r,r")
(match_operand:SI 1 "s_register_operand" "%?r,0"))
--- 1197,1203 ----
)
(define_insn "*mulsi3_compare0"
! [(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV (mult:SI
(match_operand:SI 2 "s_register_operand" "r,r")
(match_operand:SI 1 "s_register_operand" "%?r,0"))
***************
*** 1202,1208 ****
)
(define_insn "*mulsi_compare0_scratch"
! [(set (reg:CC_NOOV 24)
(compare:CC_NOOV (mult:SI
(match_operand:SI 2 "s_register_operand" "r,r")
(match_operand:SI 1 "s_register_operand" "%?r,0"))
--- 1211,1217 ----
)
(define_insn "*mulsi_compare0_scratch"
! [(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV (mult:SI
(match_operand:SI 2 "s_register_operand" "r,r")
(match_operand:SI 1 "s_register_operand" "%?r,0"))
***************
*** 1229,1235 ****
)
(define_insn "*mulsi3addsi_compare0"
! [(set (reg:CC_NOOV 24)
(compare:CC_NOOV
(plus:SI (mult:SI
(match_operand:SI 2 "s_register_operand" "r,r,r,r")
--- 1238,1244 ----
)
(define_insn "*mulsi3addsi_compare0"
! [(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV
(plus:SI (mult:SI
(match_operand:SI 2 "s_register_operand" "r,r,r,r")
***************
*** 1246,1252 ****
)
(define_insn "*mulsi3addsi_compare0_scratch"
! [(set (reg:CC_NOOV 24)
(compare:CC_NOOV
(plus:SI (mult:SI
(match_operand:SI 2 "s_register_operand" "r,r,r,r")
--- 1255,1261 ----
)
(define_insn "*mulsi3addsi_compare0_scratch"
! [(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV
(plus:SI (mult:SI
(match_operand:SI 2 "s_register_operand" "r,r,r,r")
***************
*** 1848,1854 ****
)
(define_insn "*andsi3_compare0"
! [(set (reg:CC_NOOV 24)
(compare:CC_NOOV
(and:SI (match_operand:SI 1 "s_register_operand" "r,r")
(match_operand:SI 2 "arm_not_operand" "rI,K"))
--- 1857,1863 ----
)
(define_insn "*andsi3_compare0"
! [(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV
(and:SI (match_operand:SI 1 "s_register_operand" "r,r")
(match_operand:SI 2 "arm_not_operand" "rI,K"))
***************
*** 1863,1869 ****
)
(define_insn "*andsi3_compare0_scratch"
! [(set (reg:CC_NOOV 24)
(compare:CC_NOOV
(and:SI (match_operand:SI 0 "s_register_operand" "r,r")
(match_operand:SI 1 "arm_not_operand" "rI,K"))
--- 1872,1878 ----
)
(define_insn "*andsi3_compare0_scratch"
! [(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV
(and:SI (match_operand:SI 0 "s_register_operand" "r,r")
(match_operand:SI 1 "arm_not_operand" "rI,K"))
***************
*** 1877,1883 ****
)
(define_insn "*zeroextractsi_compare0_scratch"
! [(set (reg:CC_NOOV 24)
(compare:CC_NOOV (zero_extract:SI
(match_operand:SI 0 "s_register_operand" "r")
(match_operand 1 "const_int_operand" "n")
--- 1886,1892 ----
)
(define_insn "*zeroextractsi_compare0_scratch"
! [(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV (zero_extract:SI
(match_operand:SI 0 "s_register_operand" "r")
(match_operand 1 "const_int_operand" "n")
***************
*** 2129,2135 ****
)
(define_insn "*andsi_notsi_si_compare0"
! [(set (reg:CC_NOOV 24)
(compare:CC_NOOV
(and:SI (not:SI (match_operand:SI 2 "s_register_operand" "r"))
(match_operand:SI 1 "s_register_operand" "r"))
--- 2138,2144 ----
)
(define_insn "*andsi_notsi_si_compare0"
! [(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV
(and:SI (not:SI (match_operand:SI 2 "s_register_operand" "r"))
(match_operand:SI 1 "s_register_operand" "r"))
***************
*** 2142,2148 ****
)
(define_insn "*andsi_notsi_si_compare0_scratch"
! [(set (reg:CC_NOOV 24)
(compare:CC_NOOV
(and:SI (not:SI (match_operand:SI 2 "s_register_operand" "r"))
(match_operand:SI 1 "s_register_operand" "r"))
--- 2151,2157 ----
)
(define_insn "*andsi_notsi_si_compare0_scratch"
! [(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV
(and:SI (not:SI (match_operand:SI 2 "s_register_operand" "r"))
(match_operand:SI 1 "s_register_operand" "r"))
***************
*** 2244,2250 ****
)
(define_insn "*iorsi3_compare0"
! [(set (reg:CC_NOOV 24)
(compare:CC_NOOV (ior:SI (match_operand:SI 1 "s_register_operand" "%r")
(match_operand:SI 2 "arm_rhs_operand" "rI"))
(const_int 0)))
--- 2253,2259 ----
)
(define_insn "*iorsi3_compare0"
! [(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV (ior:SI (match_operand:SI 1 "s_register_operand" "%r")
(match_operand:SI 2 "arm_rhs_operand" "rI"))
(const_int 0)))
***************
*** 2256,2262 ****
)
(define_insn "*iorsi3_compare0_scratch"
! [(set (reg:CC_NOOV 24)
(compare:CC_NOOV (ior:SI (match_operand:SI 1 "s_register_operand" "%r")
(match_operand:SI 2 "arm_rhs_operand" "rI"))
(const_int 0)))
--- 2265,2271 ----
)
(define_insn "*iorsi3_compare0_scratch"
! [(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV (ior:SI (match_operand:SI 1 "s_register_operand" "%r")
(match_operand:SI 2 "arm_rhs_operand" "rI"))
(const_int 0)))
***************
*** 2330,2336 ****
)
(define_insn "*xorsi3_compare0"
! [(set (reg:CC_NOOV 24)
(compare:CC_NOOV (xor:SI (match_operand:SI 1 "s_register_operand" "r")
(match_operand:SI 2 "arm_rhs_operand" "rI"))
(const_int 0)))
--- 2339,2345 ----
)
(define_insn "*xorsi3_compare0"
! [(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV (xor:SI (match_operand:SI 1 "s_register_operand" "r")
(match_operand:SI 2 "arm_rhs_operand" "rI"))
(const_int 0)))
***************
*** 2342,2348 ****
)
(define_insn "*xorsi3_compare0_scratch"
! [(set (reg:CC_NOOV 24)
(compare:CC_NOOV (xor:SI (match_operand:SI 0 "s_register_operand" "r")
(match_operand:SI 1 "arm_rhs_operand" "rI"))
(const_int 0)))]
--- 2351,2357 ----
)
(define_insn "*xorsi3_compare0_scratch"
! [(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV (xor:SI (match_operand:SI 0 "s_register_operand" "r")
(match_operand:SI 1 "arm_rhs_operand" "rI"))
(const_int 0)))]
***************
*** 2387,2393 ****
[(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
(smax:SI (match_operand:SI 1 "s_register_operand" "0,r,?r")
(match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
! (clobber (reg:CC 24))]
"TARGET_ARM"
"@
cmp\\t%1, %2\;movlt\\t%0, %2
--- 2396,2402 ----
[(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
(smax:SI (match_operand:SI 1 "s_register_operand" "0,r,?r")
(match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
! (clobber (reg:CC CC_REGNUM))]
"TARGET_ARM"
"@
cmp\\t%1, %2\;movlt\\t%0, %2
***************
*** 2401,2407 ****
[(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
(smin:SI (match_operand:SI 1 "s_register_operand" "0,r,?r")
(match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
! (clobber (reg:CC 24))]
"TARGET_ARM"
"@
cmp\\t%1, %2\;movge\\t%0, %2
--- 2410,2416 ----
[(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
(smin:SI (match_operand:SI 1 "s_register_operand" "0,r,?r")
(match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
! (clobber (reg:CC CC_REGNUM))]
"TARGET_ARM"
"@
cmp\\t%1, %2\;movge\\t%0, %2
***************
*** 2415,2421 ****
[(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
(umax:SI (match_operand:SI 1 "s_register_operand" "0,r,?r")
(match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
! (clobber (reg:CC 24))]
"TARGET_ARM"
"@
cmp\\t%1, %2\;movcc\\t%0, %2
--- 2424,2430 ----
[(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
(umax:SI (match_operand:SI 1 "s_register_operand" "0,r,?r")
(match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
! (clobber (reg:CC CC_REGNUM))]
"TARGET_ARM"
"@
cmp\\t%1, %2\;movcc\\t%0, %2
***************
*** 2429,2435 ****
[(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
(umin:SI (match_operand:SI 1 "s_register_operand" "0,r,?r")
(match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
! (clobber (reg:CC 24))]
"TARGET_ARM"
"@
cmp\\t%1, %2\;movcs\\t%0, %2
--- 2438,2444 ----
[(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
(umin:SI (match_operand:SI 1 "s_register_operand" "0,r,?r")
(match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
! (clobber (reg:CC CC_REGNUM))]
"TARGET_ARM"
"@
cmp\\t%1, %2\;movcs\\t%0, %2
***************
*** 2444,2450 ****
(match_operator:SI 3 "minmax_operator"
[(match_operand:SI 1 "s_register_operand" "r")
(match_operand:SI 2 "s_register_operand" "r")]))
! (clobber (reg:CC 24))]
"TARGET_ARM"
"*
operands[3] = gen_rtx (minmax_code (operands[3]), SImode, operands[1],
--- 2453,2459 ----
(match_operator:SI 3 "minmax_operator"
[(match_operand:SI 1 "s_register_operand" "r")
(match_operand:SI 2 "s_register_operand" "r")]))
! (clobber (reg:CC CC_REGNUM))]
"TARGET_ARM"
"*
operands[3] = gen_rtx (minmax_code (operands[3]), SImode, operands[1],
***************
*** 2468,2474 ****
[(match_operand:SI 2 "s_register_operand" "r,r")
(match_operand:SI 3 "arm_rhs_operand" "rI,rI")])
(match_operand:SI 1 "s_register_operand" "0,?r")]))
! (clobber (reg:CC 24))]
"TARGET_ARM
&& (GET_CODE (operands[1]) != REG
|| (REGNO(operands[1]) != FRAME_POINTER_REGNUM
--- 2477,2483 ----
[(match_operand:SI 2 "s_register_operand" "r,r")
(match_operand:SI 3 "arm_rhs_operand" "rI,rI")])
(match_operand:SI 1 "s_register_operand" "0,?r")]))
! (clobber (reg:CC CC_REGNUM))]
"TARGET_ARM
&& (GET_CODE (operands[1]) != REG
|| (REGNO(operands[1]) != FRAME_POINTER_REGNUM
***************
*** 2620,2626 ****
)
(define_insn "*shiftsi3_compare0"
! [(set (reg:CC_NOOV 24)
(compare:CC_NOOV (match_operator:SI 3 "shift_operator"
[(match_operand:SI 1 "s_register_operand" "r")
(match_operand:SI 2 "arm_rhs_operand" "rM")])
--- 2629,2635 ----
)
(define_insn "*shiftsi3_compare0"
! [(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV (match_operator:SI 3 "shift_operator"
[(match_operand:SI 1 "s_register_operand" "r")
(match_operand:SI 2 "arm_rhs_operand" "rM")])
***************
*** 2634,2640 ****
)
(define_insn "*shiftsi3_compare0_scratch"
! [(set (reg:CC_NOOV 24)
(compare:CC_NOOV (match_operator:SI 3 "shift_operator"
[(match_operand:SI 1 "s_register_operand" "r")
(match_operand:SI 2 "arm_rhs_operand" "rM")])
--- 2643,2649 ----
)
(define_insn "*shiftsi3_compare0_scratch"
! [(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV (match_operator:SI 3 "shift_operator"
[(match_operand:SI 1 "s_register_operand" "r")
(match_operand:SI 2 "arm_rhs_operand" "rM")])
***************
*** 2658,2664 ****
)
(define_insn "*notsi_shiftsi_compare0"
! [(set (reg:CC_NOOV 24)
(compare:CC_NOOV (not:SI (match_operator:SI 3 "shift_operator"
[(match_operand:SI 1 "s_register_operand" "r")
(match_operand:SI 2 "arm_rhs_operand" "rM")]))
--- 2667,2673 ----
)
(define_insn "*notsi_shiftsi_compare0"
! [(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV (not:SI (match_operator:SI 3 "shift_operator"
[(match_operand:SI 1 "s_register_operand" "r")
(match_operand:SI 2 "arm_rhs_operand" "rM")]))
***************
*** 2672,2678 ****
)
(define_insn "*not_shiftsi_compare0_scratch"
! [(set (reg:CC_NOOV 24)
(compare:CC_NOOV (not:SI (match_operator:SI 3 "shift_operator"
[(match_operand:SI 1 "s_register_operand" "r")
(match_operand:SI 2 "arm_rhs_operand" "rM")]))
--- 2681,2687 ----
)
(define_insn "*not_shiftsi_compare0_scratch"
! [(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV (not:SI (match_operator:SI 3 "shift_operator"
[(match_operand:SI 1 "s_register_operand" "r")
(match_operand:SI 2 "arm_rhs_operand" "rM")]))
***************
*** 2720,2726 ****
[(parallel
[(set (match_operand:DI 0 "s_register_operand" "")
(neg:DI (match_operand:DI 1 "s_register_operand" "")))
! (clobber (reg:CC 24))])]
"TARGET_EITHER"
"
if (TARGET_THUMB)
--- 2729,2735 ----
[(parallel
[(set (match_operand:DI 0 "s_register_operand" "")
(neg:DI (match_operand:DI 1 "s_register_operand" "")))
! (clobber (reg:CC CC_REGNUM))])]
"TARGET_EITHER"
"
if (TARGET_THUMB)
***************
*** 2736,2742 ****
(define_insn "*arm_negdi2"
[(set (match_operand:DI 0 "s_register_operand" "=&r,r")
(neg:DI (match_operand:DI 1 "s_register_operand" "?r,0")))
! (clobber (reg:CC 24))]
"TARGET_ARM"
"rsbs\\t%Q0, %Q1, #0\;rsc\\t%R0, %R1, #0"
[(set_attr "conds" "clob")
--- 2745,2751 ----
(define_insn "*arm_negdi2"
[(set (match_operand:DI 0 "s_register_operand" "=&r,r")
(neg:DI (match_operand:DI 1 "s_register_operand" "?r,0")))
! (clobber (reg:CC CC_REGNUM))]
"TARGET_ARM"
"rsbs\\t%Q0, %Q1, #0\;rsc\\t%R0, %R1, #0"
[(set_attr "conds" "clob")
***************
*** 2746,2752 ****
(define_insn "*thumb_negdi2"
[(set (match_operand:DI 0 "register_operand" "=&l")
(neg:DI (match_operand:DI 1 "register_operand" "l")))
! (clobber (reg:CC 24))]
"TARGET_THUMB"
"mov\\t%R0, #0\;neg\\t%Q0, %Q1\;sbc\\t%R0, %R1"
[(set_attr "length" "6")]
--- 2755,2761 ----
(define_insn "*thumb_negdi2"
[(set (match_operand:DI 0 "register_operand" "=&l")
(neg:DI (match_operand:DI 1 "register_operand" "l")))
! (clobber (reg:CC CC_REGNUM))]
"TARGET_THUMB"
"mov\\t%R0, #0\;neg\\t%Q0, %Q1\;sbc\\t%R0, %R1"
[(set_attr "length" "6")]
***************
*** 2820,2826 ****
(define_insn "abssi2"
[(set (match_operand:SI 0 "s_register_operand" "=r,&r")
(abs:SI (match_operand:SI 1 "s_register_operand" "0,r")))
! (clobber (reg:CC 24))]
"TARGET_ARM"
"@
cmp\\t%0, #0\;rsblt\\t%0, %0, #0
--- 2829,2835 ----
(define_insn "abssi2"
[(set (match_operand:SI 0 "s_register_operand" "=r,&r")
(abs:SI (match_operand:SI 1 "s_register_operand" "0,r")))
! (clobber (reg:CC CC_REGNUM))]
"TARGET_ARM"
"@
cmp\\t%0, #0\;rsblt\\t%0, %0, #0
***************
*** 2833,2839 ****
(define_insn "*neg_abssi2"
[(set (match_operand:SI 0 "s_register_operand" "=r,&r")
(neg:SI (abs:SI (match_operand:SI 1 "s_register_operand" "0,r"))))
! (clobber (reg:CC 24))]
"TARGET_ARM"
"@
cmp\\t%0, #0\;rsbgt\\t%0, %0, #0
--- 2842,2848 ----
(define_insn "*neg_abssi2"
[(set (match_operand:SI 0 "s_register_operand" "=r,&r")
(neg:SI (abs:SI (match_operand:SI 1 "s_register_operand" "0,r"))))
! (clobber (reg:CC CC_REGNUM))]
"TARGET_ARM"
"@
cmp\\t%0, #0\;rsbgt\\t%0, %0, #0
***************
*** 3010,3016 ****
)
(define_insn "*notsi_compare0"
! [(set (reg:CC_NOOV 24)
(compare:CC_NOOV (not:SI (match_operand:SI 1 "s_register_operand" "r"))
(const_int 0)))
(set (match_operand:SI 0 "s_register_operand" "=r")
--- 3019,3025 ----
)
(define_insn "*notsi_compare0"
! [(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV (not:SI (match_operand:SI 1 "s_register_operand" "r"))
(const_int 0)))
(set (match_operand:SI 0 "s_register_operand" "=r")
***************
*** 3021,3027 ****
)
(define_insn "*notsi_compare0_scratch"
! [(set (reg:CC_NOOV 24)
(compare:CC_NOOV (not:SI (match_operand:SI 1 "s_register_operand" "r"))
(const_int 0)))
(clobber (match_scratch:SI 0 "=r"))]
--- 3030,3036 ----
)
(define_insn "*notsi_compare0_scratch"
! [(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV (not:SI (match_operand:SI 1 "s_register_operand" "r"))
(const_int 0)))
(clobber (match_scratch:SI 0 "=r"))]
***************
*** 3388,3394 ****
)
(define_insn "*compareqi_eq0"
! [(set (reg:CC_Z 24)
(compare:CC_Z (match_operand:QI 0 "s_register_operand" "r")
(const_int 0)))]
"TARGET_ARM"
--- 3397,3403 ----
)
(define_insn "*compareqi_eq0"
! [(set (reg:CC_Z CC_REGNUM)
(compare:CC_Z (match_operand:QI 0 "s_register_operand" "r")
(const_int 0)))]
"TARGET_ARM"
***************
*** 4237,4243 ****
;; result is being tested against zero.
(define_insn "*movsi_compare0"
! [(set (reg:CC 24)
(compare:CC (match_operand:SI 1 "s_register_operand" "0,r")
(const_int 0)))
(set (match_operand:SI 0 "s_register_operand" "=r,r")
--- 4246,4252 ----
;; result is being tested against zero.
(define_insn "*movsi_compare0"
! [(set (reg:CC CC_REGNUM)
(compare:CC (match_operand:SI 1 "s_register_operand" "0,r")
(const_int 0)))
(set (match_operand:SI 0 "s_register_operand" "=r,r")
***************
*** 5202,5215 ****
(use (match_operand:SI 2 "" ""))])]
"TARGET_ARM"
"
! /* Support only fixed point registers */
if (GET_CODE (operands[2]) != CONST_INT
|| INTVAL (operands[2]) > 14
|| INTVAL (operands[2]) < 2
|| GET_CODE (operands[1]) != MEM
|| GET_CODE (operands[0]) != REG
! || REGNO (operands[0]) > 14
! || REGNO (operands[0]) + INTVAL (operands[2]) > 15)
FAIL;
operands[3]
--- 5211,5224 ----
(use (match_operand:SI 2 "" ""))])]
"TARGET_ARM"
"
! /* Support only fixed point registers. */
if (GET_CODE (operands[2]) != CONST_INT
|| INTVAL (operands[2]) > 14
|| INTVAL (operands[2]) < 2
|| GET_CODE (operands[1]) != MEM
|| GET_CODE (operands[0]) != REG
! || REGNO (operands[0]) > (LAST_ARM_REGNUM - 1)
! || REGNO (operands[0]) + INTVAL (operands[2]) > LAST_ARM_REGNUM)
FAIL;
operands[3]
***************
*** 5284,5291 ****
|| INTVAL (operands[2]) < 2
|| GET_CODE (operands[1]) != REG
|| GET_CODE (operands[0]) != MEM
! || REGNO (operands[1]) > 14
! || REGNO (operands[1]) + INTVAL (operands[2]) > 15)
FAIL;
operands[3]
--- 5293,5300 ----
|| INTVAL (operands[2]) < 2
|| GET_CODE (operands[1]) != REG
|| GET_CODE (operands[0]) != MEM
! || REGNO (operands[1]) > (LAST_ARM_REGNUM - 1)
! || REGNO (operands[1]) + INTVAL (operands[2]) > LAST_ARM_REGNUM)
FAIL;
operands[3]
***************
*** 5552,5558 ****
)
(define_insn "*arm_cmpsi_insn"
! [(set (reg:CC 24)
(compare:CC (match_operand:SI 0 "s_register_operand" "r,r")
(match_operand:SI 1 "arm_add_operand" "rI,L")))]
"TARGET_ARM"
--- 5561,5567 ----
)
(define_insn "*arm_cmpsi_insn"
! [(set (reg:CC CC_REGNUM)
(compare:CC (match_operand:SI 0 "s_register_operand" "r,r")
(match_operand:SI 1 "arm_add_operand" "rI,L")))]
"TARGET_ARM"
***************
*** 5563,5569 ****
)
(define_insn "*cmpsi_shiftsi"
! [(set (reg:CC 24)
(compare:CC (match_operand:SI 0 "s_register_operand" "r")
(match_operator:SI 3 "shift_operator"
[(match_operand:SI 1 "s_register_operand" "r")
--- 5572,5578 ----
)
(define_insn "*cmpsi_shiftsi"
! [(set (reg:CC CC_REGNUM)
(compare:CC (match_operand:SI 0 "s_register_operand" "r")
(match_operator:SI 3 "shift_operator"
[(match_operand:SI 1 "s_register_operand" "r")
***************
*** 5575,5581 ****
)
(define_insn "*cmpsi_shiftsi_swp"
! [(set (reg:CC_SWP 24)
(compare:CC_SWP (match_operator:SI 3 "shift_operator"
[(match_operand:SI 1 "s_register_operand" "r")
(match_operand:SI 2 "reg_or_int_operand" "rM")])
--- 5584,5590 ----
)
(define_insn "*cmpsi_shiftsi_swp"
! [(set (reg:CC_SWP CC_REGNUM)
(compare:CC_SWP (match_operator:SI 3 "shift_operator"
[(match_operand:SI 1 "s_register_operand" "r")
(match_operand:SI 2 "reg_or_int_operand" "rM")])
***************
*** 5587,5593 ****
)
(define_insn "*cmpsi_neg_shiftsi"
! [(set (reg:CC 24)
(compare:CC (match_operand:SI 0 "s_register_operand" "r")
(neg:SI (match_operator:SI 3 "shift_operator"
[(match_operand:SI 1 "s_register_operand" "r")
--- 5596,5602 ----
)
(define_insn "*cmpsi_neg_shiftsi"
! [(set (reg:CC CC_REGNUM)
(compare:CC (match_operand:SI 0 "s_register_operand" "r")
(neg:SI (match_operator:SI 3 "shift_operator"
[(match_operand:SI 1 "s_register_operand" "r")
***************
*** 5599,5605 ****
)
(define_insn "*cmpsf_insn"
! [(set (reg:CCFP 24)
(compare:CCFP (match_operand:SF 0 "s_register_operand" "f,f")
(match_operand:SF 1 "fpu_add_operand" "fG,H")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
--- 5608,5614 ----
)
(define_insn "*cmpsf_insn"
! [(set (reg:CCFP CC_REGNUM)
(compare:CCFP (match_operand:SF 0 "s_register_operand" "f,f")
(match_operand:SF 1 "fpu_add_operand" "fG,H")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
***************
*** 5611,5617 ****
)
(define_insn "*cmpdf_insn"
! [(set (reg:CCFP 24)
(compare:CCFP (match_operand:DF 0 "s_register_operand" "f,f")
(match_operand:DF 1 "fpu_add_operand" "fG,H")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
--- 5620,5626 ----
)
(define_insn "*cmpdf_insn"
! [(set (reg:CCFP CC_REGNUM)
(compare:CCFP (match_operand:DF 0 "s_register_operand" "f,f")
(match_operand:DF 1 "fpu_add_operand" "fG,H")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
***************
*** 5623,5629 ****
)
(define_insn "*cmpesfdf_df"
! [(set (reg:CCFP 24)
(compare:CCFP (float_extend:DF
(match_operand:SF 0 "s_register_operand" "f,f"))
(match_operand:DF 1 "fpu_add_operand" "fG,H")))]
--- 5632,5638 ----
)
(define_insn "*cmpesfdf_df"
! [(set (reg:CCFP CC_REGNUM)
(compare:CCFP (float_extend:DF
(match_operand:SF 0 "s_register_operand" "f,f"))
(match_operand:DF 1 "fpu_add_operand" "fG,H")))]
***************
*** 5636,5642 ****
)
(define_insn "*cmpdf_esfdf"
! [(set (reg:CCFP 24)
(compare:CCFP (match_operand:DF 0 "s_register_operand" "f")
(float_extend:DF
(match_operand:SF 1 "s_register_operand" "f"))))]
--- 5645,5651 ----
)
(define_insn "*cmpdf_esfdf"
! [(set (reg:CCFP CC_REGNUM)
(compare:CCFP (match_operand:DF 0 "s_register_operand" "f")
(float_extend:DF
(match_operand:SF 1 "s_register_operand" "f"))))]
***************
*** 5647,5653 ****
)
(define_insn "*cmpxf_insn"
! [(set (reg:CCFP 24)
(compare:CCFP (match_operand:XF 0 "s_register_operand" "f,f")
(match_operand:XF 1 "fpu_add_operand" "fG,H")))]
"TARGET_ARM && ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT"
--- 5656,5662 ----
)
(define_insn "*cmpxf_insn"
! [(set (reg:CCFP CC_REGNUM)
(compare:CCFP (match_operand:XF 0 "s_register_operand" "f,f")
(match_operand:XF 1 "fpu_add_operand" "fG,H")))]
"TARGET_ARM && ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT"
***************
*** 5659,5665 ****
)
(define_insn "*cmpsf_trap"
! [(set (reg:CCFPE 24)
(compare:CCFPE (match_operand:SF 0 "s_register_operand" "f,f")
(match_operand:SF 1 "fpu_add_operand" "fG,H")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
--- 5668,5674 ----
)
(define_insn "*cmpsf_trap"
! [(set (reg:CCFPE CC_REGNUM)
(compare:CCFPE (match_operand:SF 0 "s_register_operand" "f,f")
(match_operand:SF 1 "fpu_add_operand" "fG,H")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
***************
*** 5671,5677 ****
)
(define_insn "*cmpdf_trap"
! [(set (reg:CCFPE 24)
(compare:CCFPE (match_operand:DF 0 "s_register_operand" "f,f")
(match_operand:DF 1 "fpu_add_operand" "fG,H")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
--- 5680,5686 ----
)
(define_insn "*cmpdf_trap"
! [(set (reg:CCFPE CC_REGNUM)
(compare:CCFPE (match_operand:DF 0 "s_register_operand" "f,f")
(match_operand:DF 1 "fpu_add_operand" "fG,H")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
***************
*** 5683,5689 ****
)
(define_insn "*cmp_esfdf_df_trap"
! [(set (reg:CCFPE 24)
(compare:CCFPE (float_extend:DF
(match_operand:SF 0 "s_register_operand" "f,f"))
(match_operand:DF 1 "fpu_add_operand" "fG,H")))]
--- 5692,5698 ----
)
(define_insn "*cmp_esfdf_df_trap"
! [(set (reg:CCFPE CC_REGNUM)
(compare:CCFPE (float_extend:DF
(match_operand:SF 0 "s_register_operand" "f,f"))
(match_operand:DF 1 "fpu_add_operand" "fG,H")))]
***************
*** 5696,5702 ****
)
(define_insn "*cmp_df_esfdf_trap"
! [(set (reg:CCFPE 24)
(compare:CCFPE (match_operand:DF 0 "s_register_operand" "f")
(float_extend:DF
(match_operand:SF 1 "s_register_operand" "f"))))]
--- 5705,5711 ----
)
(define_insn "*cmp_df_esfdf_trap"
! [(set (reg:CCFPE CC_REGNUM)
(compare:CCFPE (match_operand:DF 0 "s_register_operand" "f")
(float_extend:DF
(match_operand:SF 1 "s_register_operand" "f"))))]
***************
*** 5707,5713 ****
)
(define_insn "*cmpxf_trap"
! [(set (reg:CCFPE 24)
(compare:CCFPE (match_operand:XF 0 "s_register_operand" "f,f")
(match_operand:XF 1 "fpu_add_operand" "fG,H")))]
"TARGET_ARM && ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT"
--- 5716,5722 ----
)
(define_insn "*cmpxf_trap"
! [(set (reg:CCFPE CC_REGNUM)
(compare:CCFPE (match_operand:XF 0 "s_register_operand" "f,f")
(match_operand:XF 1 "fpu_add_operand" "fG,H")))]
"TARGET_ARM && ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT"
***************
*** 6364,6370 ****
[(parallel [(call (match_operand 0 "memory_operand" "")
(match_operand 1 "general_operand" ""))
(use (match_operand 2 "" ""))
! (clobber (reg:SI 14))])]
"TARGET_EITHER"
"
{
--- 6373,6379 ----
[(parallel [(call (match_operand 0 "memory_operand" "")
(match_operand 1 "general_operand" ""))
(use (match_operand 2 "" ""))
! (clobber (reg:SI LR_REGNUM))])]
"TARGET_EITHER"
"
{
***************
*** 6396,6402 ****
[(call (mem:SI (match_operand:SI 0 "s_register_operand" "r"))
(match_operand 1 "" ""))
(use (match_operand 2 "" ""))
! (clobber (reg:SI 14))]
"TARGET_ARM"
"*
return output_call (operands);
--- 6405,6411 ----
[(call (mem:SI (match_operand:SI 0 "s_register_operand" "r"))
(match_operand 1 "" ""))
(use (match_operand 2 "" ""))
! (clobber (reg:SI LR_REGNUM))]
"TARGET_ARM"
"*
return output_call (operands);
***************
*** 6410,6416 ****
[(call (mem:SI (match_operand:SI 0 "memory_operand" "m"))
(match_operand 1 "" ""))
(use (match_operand 2 "" ""))
! (clobber (reg:SI 14))]
"TARGET_ARM"
"*
return output_call_mem (operands);
--- 6419,6425 ----
[(call (mem:SI (match_operand:SI 0 "memory_operand" "m"))
(match_operand 1 "" ""))
(use (match_operand 2 "" ""))
! (clobber (reg:SI LR_REGNUM))]
"TARGET_ARM"
"*
return output_call_mem (operands);
***************
*** 6423,6429 ****
[(call (mem:SI (match_operand:SI 0 "register_operand" "l*r"))
(match_operand 1 "" ""))
(use (match_operand 2 "" ""))
! (clobber (reg:SI 14))]
"TARGET_THUMB"
"*
{
--- 6432,6438 ----
[(call (mem:SI (match_operand:SI 0 "register_operand" "l*r"))
(match_operand 1 "" ""))
(use (match_operand 2 "" ""))
! (clobber (reg:SI LR_REGNUM))]
"TARGET_THUMB"
"*
{
***************
*** 6440,6446 ****
(call (mem:SI (match_operand:SI 1 "register_operand" "l*r"))
(match_operand 2 "" "")))
(use (match_operand 3 "" ""))
! (clobber (reg:SI 14))]
"TARGET_THUMB"
"*
{
--- 6449,6455 ----
(call (mem:SI (match_operand:SI 1 "register_operand" "l*r"))
(match_operand 2 "" "")))
(use (match_operand 3 "" ""))
! (clobber (reg:SI LR_REGNUM))]
"TARGET_THUMB"
"*
{
***************
*** 6457,6463 ****
(call (match_operand 1 "memory_operand" "")
(match_operand 2 "general_operand" "")))
(use (match_operand 3 "" ""))
! (clobber (reg:SI 14))])]
"TARGET_EITHER"
"
{
--- 6466,6472 ----
(call (match_operand 1 "memory_operand" "")
(match_operand 2 "general_operand" "")))
(use (match_operand 3 "" ""))
! (clobber (reg:SI LR_REGNUM))])]
"TARGET_EITHER"
"
{
***************
*** 6479,6485 ****
(call (mem:SI (match_operand:SI 1 "s_register_operand" "r,r"))
(match_operand 2 "" "")))
(use (match_operand 3 "" ""))
! (clobber (reg:SI 14))]
"TARGET_ARM"
"*
return output_call (&operands[1]);
--- 6488,6494 ----
(call (mem:SI (match_operand:SI 1 "s_register_operand" "r,r"))
(match_operand 2 "" "")))
(use (match_operand 3 "" ""))
! (clobber (reg:SI LR_REGNUM))]
"TARGET_ARM"
"*
return output_call (&operands[1]);
***************
*** 6493,6499 ****
(call (mem:SI (match_operand:SI 1 "memory_operand" "m,m"))
(match_operand 2 "" "")))
(use (match_operand 3 "" ""))
! (clobber (reg:SI 14))]
"TARGET_ARM && (!CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))"
"*
return output_call_mem (&operands[1]);
--- 6502,6508 ----
(call (mem:SI (match_operand:SI 1 "memory_operand" "m,m"))
(match_operand 2 "" "")))
(use (match_operand 3 "" ""))
! (clobber (reg:SI LR_REGNUM))]
"TARGET_ARM && (!CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))"
"*
return output_call_mem (&operands[1]);
***************
*** 6509,6515 ****
[(call (mem:SI (match_operand:SI 0 "" "X"))
(match_operand 1 "" ""))
(use (match_operand 2 "" ""))
! (clobber (reg:SI 14))]
"TARGET_ARM
&& (GET_CODE (operands[0]) == SYMBOL_REF)
&& !arm_is_longcall_p (operands[0], INTVAL (operands[2]), 1)"
--- 6518,6524 ----
[(call (mem:SI (match_operand:SI 0 "" "X"))
(match_operand 1 "" ""))
(use (match_operand 2 "" ""))
! (clobber (reg:SI LR_REGNUM))]
"TARGET_ARM
&& (GET_CODE (operands[0]) == SYMBOL_REF)
&& !arm_is_longcall_p (operands[0], INTVAL (operands[2]), 1)"
***************
*** 6525,6531 ****
(call (mem:SI (match_operand:SI 1 "" "X,X"))
(match_operand:SI 2 "" "")))
(use (match_operand 3 "" ""))
! (clobber (reg:SI 14))]
"TARGET_ARM
&& (GET_CODE (operands[1]) == SYMBOL_REF)
&& !arm_is_longcall_p (operands[1], INTVAL (operands[3]), 1)"
--- 6534,6540 ----
(call (mem:SI (match_operand:SI 1 "" "X,X"))
(match_operand:SI 2 "" "")))
(use (match_operand 3 "" ""))
! (clobber (reg:SI LR_REGNUM))]
"TARGET_ARM
&& (GET_CODE (operands[1]) == SYMBOL_REF)
&& !arm_is_longcall_p (operands[1], INTVAL (operands[3]), 1)"
***************
*** 6540,6546 ****
[(call (mem:SI (match_operand:SI 0 "" "X"))
(match_operand:SI 1 "" ""))
(use (match_operand 2 "" ""))
! (clobber (reg:SI 14))]
"TARGET_THUMB
&& operands[2] == const0_rtx && (GET_CODE (operands[0]) == SYMBOL_REF)"
"bl\\t%a0"
--- 6549,6555 ----
[(call (mem:SI (match_operand:SI 0 "" "X"))
(match_operand:SI 1 "" ""))
(use (match_operand 2 "" ""))
! (clobber (reg:SI LR_REGNUM))]
"TARGET_THUMB
&& operands[2] == const0_rtx && (GET_CODE (operands[0]) == SYMBOL_REF)"
"bl\\t%a0"
***************
*** 6553,6559 ****
(call (mem:SI (match_operand 1 "" "X"))
(match_operand 2 "" "")))
(use (match_operand 3 "" ""))
! (clobber (reg:SI 14))]
"TARGET_THUMB
&& operands[3] == const0_rtx && (GET_CODE (operands[1]) == SYMBOL_REF)"
"bl\\t%a1"
--- 6562,6568 ----
(call (mem:SI (match_operand 1 "" "X"))
(match_operand 2 "" "")))
(use (match_operand 3 "" ""))
! (clobber (reg:SI LR_REGNUM))]
"TARGET_THUMB
&& operands[3] == const0_rtx && (GET_CODE (operands[1]) == SYMBOL_REF)"
"bl\\t%a1"
***************
*** 6747,6753 ****
(mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
(label_ref (match_operand 2 "" ""))))
(label_ref (match_operand 3 "" ""))))
! (clobber (reg:CC 24))
(use (label_ref (match_dup 2)))])]
"TARGET_ARM"
"*
--- 6756,6762 ----
(mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
(label_ref (match_operand 2 "" ""))))
(label_ref (match_operand 3 "" ""))))
! (clobber (reg:CC CC_REGNUM))
(use (label_ref (match_dup 2)))])]
"TARGET_ARM"
"*
***************
*** 6828,6834 ****
)
(define_insn "*arith_shiftsi_compare0"
! [(set (reg:CC_NOOV 24)
(compare:CC_NOOV (match_operator:SI 1 "shiftable_operator"
[(match_operator:SI 3 "shift_operator"
[(match_operand:SI 4 "s_register_operand" "r")
--- 6837,6843 ----
)
(define_insn "*arith_shiftsi_compare0"
! [(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV (match_operator:SI 1 "shiftable_operator"
[(match_operator:SI 3 "shift_operator"
[(match_operand:SI 4 "s_register_operand" "r")
***************
*** 6845,6851 ****
)
(define_insn "*arith_shiftsi_compare0_scratch"
! [(set (reg:CC_NOOV 24)
(compare:CC_NOOV (match_operator:SI 1 "shiftable_operator"
[(match_operator:SI 3 "shift_operator"
[(match_operand:SI 4 "s_register_operand" "r")
--- 6854,6860 ----
)
(define_insn "*arith_shiftsi_compare0_scratch"
! [(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV (match_operator:SI 1 "shiftable_operator"
[(match_operator:SI 3 "shift_operator"
[(match_operand:SI 4 "s_register_operand" "r")
***************
*** 6872,6878 ****
)
(define_insn "*sub_shiftsi_compare0"
! [(set (reg:CC_NOOV 24)
(compare:CC_NOOV
(minus:SI (match_operand:SI 1 "s_register_operand" "r")
(match_operator:SI 2 "shift_operator"
--- 6881,6887 ----
)
(define_insn "*sub_shiftsi_compare0"
! [(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV
(minus:SI (match_operand:SI 1 "s_register_operand" "r")
(match_operator:SI 2 "shift_operator"
***************
*** 6889,6895 ****
)
(define_insn "*sub_shiftsi_compare0_scratch"
! [(set (reg:CC_NOOV 24)
(compare:CC_NOOV
(minus:SI (match_operand:SI 1 "s_register_operand" "r")
(match_operator:SI 2 "shift_operator"
--- 6898,6904 ----
)
(define_insn "*sub_shiftsi_compare0_scratch"
! [(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV
(minus:SI (match_operand:SI 1 "s_register_operand" "r")
(match_operator:SI 2 "shift_operator"
***************
*** 6931,6937 ****
)
(define_insn "*reload_mulsi_compare0"
! [(set (reg:CC_NOOV 24)
(compare:CC_NOOV (plus:SI
(plus:SI
(match_operator:SI 5 "shift_operator"
--- 6940,6946 ----
)
(define_insn "*reload_mulsi_compare0"
! [(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV (plus:SI
(plus:SI
(match_operator:SI 5 "shift_operator"
***************
*** 6954,6960 ****
)
(define_insn "*reload_mulsi_compare0_scratch"
! [(set (reg:CC_NOOV 24)
(compare:CC_NOOV (plus:SI
(plus:SI
(match_operator:SI 5 "shift_operator"
--- 6963,6969 ----
)
(define_insn "*reload_mulsi_compare0_scratch"
! [(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV (plus:SI
(plus:SI
(match_operator:SI 5 "shift_operator"
***************
*** 6994,7000 ****
)
(define_insn "*reload_muladdsi_compare0"
! [(set (reg:CC_NOOV 24)
(compare:CC_NOOV (plus:SI (plus:SI (mult:SI
(match_operand:SI 3 "" "r")
(match_operand:SI 4 "" "r"))
--- 7003,7009 ----
)
(define_insn "*reload_muladdsi_compare0"
! [(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV (plus:SI (plus:SI (mult:SI
(match_operand:SI 3 "" "r")
(match_operand:SI 4 "" "r"))
***************
*** 7016,7022 ****
)
(define_insn "*reload_muladdsi_compare0_scratch"
! [(set (reg:CC_NOOV 24)
(compare:CC_NOOV (plus:SI (plus:SI (mult:SI
(match_operand:SI 3 "" "r")
(match_operand:SI 4 "" "r"))
--- 7025,7031 ----
)
(define_insn "*reload_muladdsi_compare0_scratch"
! [(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV (plus:SI (plus:SI (mult:SI
(match_operand:SI 3 "" "r")
(match_operand:SI 4 "" "r"))
***************
*** 7065,7071 ****
(match_operator:SI 1 "arm_comparison_operator"
[(match_operand:SI 2 "s_register_operand" "r,r")
(match_operand:SI 3 "arm_add_operand" "rI,L")]))
! (clobber (reg:CC 24))]
"TARGET_ARM"
"*
if (GET_CODE (operands[1]) == LT && operands[3] == const0_rtx)
--- 7074,7080 ----
(match_operator:SI 1 "arm_comparison_operator"
[(match_operand:SI 2 "s_register_operand" "r,r")
(match_operand:SI 3 "arm_add_operand" "rI,L")]))
! (clobber (reg:CC CC_REGNUM))]
"TARGET_ARM"
"*
if (GET_CODE (operands[1]) == LT && operands[3] == const0_rtx)
***************
*** 7125,7131 ****
[(match_operand:SI 2 "s_register_operand" "r,r")
(match_operand:SI 3 "arm_rhs_operand" "rI,rI")])
(match_operand:SI 1 "s_register_operand" "0,?r")]))
! (clobber (reg:CC 24))]
"TARGET_ARM"
"*
if (GET_CODE (operands[4]) == LT && operands[3] == const0_rtx)
--- 7134,7140 ----
[(match_operand:SI 2 "s_register_operand" "r,r")
(match_operand:SI 3 "arm_rhs_operand" "rI,rI")])
(match_operand:SI 1 "s_register_operand" "0,?r")]))
! (clobber (reg:CC CC_REGNUM))]
"TARGET_ARM"
"*
if (GET_CODE (operands[4]) == LT && operands[3] == const0_rtx)
***************
*** 7150,7156 ****
(match_operator:SI 4 "arm_comparison_operator"
[(match_operand:SI 2 "s_register_operand" "r,r")
(match_operand:SI 3 "arm_rhs_operand" "rI,rI")])))
! (clobber (reg:CC 24))]
"TARGET_ARM"
"*
output_asm_insn (\"cmp\\t%2, %3\", operands);
--- 7159,7165 ----
(match_operator:SI 4 "arm_comparison_operator"
[(match_operand:SI 2 "s_register_operand" "r,r")
(match_operand:SI 3 "arm_rhs_operand" "rI,rI")])))
! (clobber (reg:CC CC_REGNUM))]
"TARGET_ARM"
"*
output_asm_insn (\"cmp\\t%2, %3\", operands);
***************
*** 7238,7244 ****
(neg:SI (match_operator 3 "arm_comparison_operator"
[(match_operand:SI 1 "s_register_operand" "r")
(match_operand:SI 2 "arm_rhs_operand" "rI")])))
! (clobber (reg:CC 24))]
"TARGET_ARM"
"*
if (GET_CODE (operands[3]) == LT && operands[3] == const0_rtx)
--- 7247,7253 ----
(neg:SI (match_operator 3 "arm_comparison_operator"
[(match_operand:SI 1 "s_register_operand" "r")
(match_operand:SI 2 "arm_rhs_operand" "rI")])))
! (clobber (reg:CC CC_REGNUM))]
"TARGET_ARM"
"*
if (GET_CODE (operands[3]) == LT && operands[3] == const0_rtx)
***************
*** 7266,7272 ****
(match_operand:SI 4 "arm_add_operand" "rIL,rIL,rIL")])
(match_operand:SI 1 "arm_rhs_operand" "0,rI,?rI")
(match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
! (clobber (reg:CC 24))]
"TARGET_ARM"
"*
if (GET_CODE (operands[5]) == LT
--- 7275,7281 ----
(match_operand:SI 4 "arm_add_operand" "rIL,rIL,rIL")])
(match_operand:SI 1 "arm_rhs_operand" "0,rI,?rI")
(match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
! (clobber (reg:CC CC_REGNUM))]
"TARGET_ARM"
"*
if (GET_CODE (operands[5]) == LT
***************
*** 7330,7336 ****
(match_operand:SI 2 "s_register_operand" "r,r")
(match_operand:SI 3 "arm_add_operand" "rIL,rIL"))
(match_operand:SI 1 "arm_rhs_operand" "0,?rI")))
! (clobber (reg:CC 24))]
"TARGET_ARM"
"#"
[(set_attr "conds" "clob")
--- 7339,7345 ----
(match_operand:SI 2 "s_register_operand" "r,r")
(match_operand:SI 3 "arm_add_operand" "rIL,rIL"))
(match_operand:SI 1 "arm_rhs_operand" "0,?rI")))
! (clobber (reg:CC CC_REGNUM))]
"TARGET_ARM"
"#"
[(set_attr "conds" "clob")
***************
*** 7366,7372 ****
(plus:SI
(match_operand:SI 2 "s_register_operand" "r,r")
(match_operand:SI 3 "arm_add_operand" "rIL,rIL"))))
! (clobber (reg:CC 24))]
"TARGET_ARM"
"#"
[(set_attr "conds" "clob")
--- 7375,7381 ----
(plus:SI
(match_operand:SI 2 "s_register_operand" "r,r")
(match_operand:SI 3 "arm_add_operand" "rIL,rIL"))))
! (clobber (reg:CC CC_REGNUM))]
"TARGET_ARM"
"#"
[(set_attr "conds" "clob")
***************
*** 7404,7410 ****
(match_operator:SI 7 "shiftable_operator"
[(match_operand:SI 3 "s_register_operand" "r")
(match_operand:SI 4 "arm_rhs_operand" "rI")])))
! (clobber (reg:CC 24))]
"TARGET_ARM"
"#"
[(set_attr "conds" "clob")
--- 7413,7419 ----
(match_operator:SI 7 "shiftable_operator"
[(match_operand:SI 3 "s_register_operand" "r")
(match_operand:SI 4 "arm_rhs_operand" "rI")])))
! (clobber (reg:CC CC_REGNUM))]
"TARGET_ARM"
"#"
[(set_attr "conds" "clob")
***************
*** 7436,7442 ****
[(match_operand:SI 4 "s_register_operand" "r,r")
(match_operand:SI 5 "arm_rhs_operand" "rI,rI")])
(match_operand:SI 1 "arm_rhs_operand" "0,?rI")))
! (clobber (reg:CC 24))]
"TARGET_ARM"
"*
/* If we have an operation where (op x 0) is the identity operation and
--- 7445,7451 ----
[(match_operand:SI 4 "s_register_operand" "r,r")
(match_operand:SI 5 "arm_rhs_operand" "rI,rI")])
(match_operand:SI 1 "arm_rhs_operand" "0,?rI")))
! (clobber (reg:CC CC_REGNUM))]
"TARGET_ARM"
"*
/* If we have an operation where (op x 0) is the identity operation and
***************
*** 7494,7500 ****
(match_operator:SI 7 "shiftable_operator"
[(match_operand:SI 2 "s_register_operand" "r,r")
(match_operand:SI 3 "arm_rhs_operand" "rI,rI")])))
! (clobber (reg:CC 24))]
"TARGET_ARM"
"*
/* If we have an operation where (op x 0) is the identity operation and
--- 7503,7509 ----
(match_operator:SI 7 "shiftable_operator"
[(match_operand:SI 2 "s_register_operand" "r,r")
(match_operand:SI 3 "arm_rhs_operand" "rI,rI")])))
! (clobber (reg:CC CC_REGNUM))]
"TARGET_ARM"
"*
/* If we have an operation where (op x 0) is the identity operation and
***************
*** 7554,7560 ****
(match_operand:SI 1 "arm_not_operand" "0,?rIK")
(not:SI
(match_operand:SI 2 "s_register_operand" "r,r"))))
! (clobber (reg:CC 24))]
"TARGET_ARM"
"#"
[(set_attr "conds" "clob")
--- 7563,7569 ----
(match_operand:SI 1 "arm_not_operand" "0,?rIK")
(not:SI
(match_operand:SI 2 "s_register_operand" "r,r"))))
! (clobber (reg:CC CC_REGNUM))]
"TARGET_ARM"
"#"
[(set_attr "conds" "clob")
***************
*** 7586,7592 ****
(not:SI
(match_operand:SI 2 "s_register_operand" "r,r"))
(match_operand:SI 1 "arm_not_operand" "0,?rIK")))
! (clobber (reg:CC 24))]
"TARGET_ARM"
"#"
[(set_attr "conds" "clob")
--- 7595,7601 ----
(not:SI
(match_operand:SI 2 "s_register_operand" "r,r"))
(match_operand:SI 1 "arm_not_operand" "0,?rIK")))
! (clobber (reg:CC CC_REGNUM))]
"TARGET_ARM"
"#"
[(set_attr "conds" "clob")
***************
*** 7619,7625 ****
[(match_operand:SI 2 "s_register_operand" "r,r")
(match_operand:SI 3 "arm_rhs_operand" "rM,rM")])
(match_operand:SI 1 "arm_not_operand" "0,?rIK")))
! (clobber (reg:CC 24))]
"TARGET_ARM"
"#"
[(set_attr "conds" "clob")
--- 7628,7634 ----
[(match_operand:SI 2 "s_register_operand" "r,r")
(match_operand:SI 3 "arm_rhs_operand" "rM,rM")])
(match_operand:SI 1 "arm_not_operand" "0,?rIK")))
! (clobber (reg:CC CC_REGNUM))]
"TARGET_ARM"
"#"
[(set_attr "conds" "clob")
***************
*** 7654,7660 ****
(match_operator:SI 7 "shift_operator"
[(match_operand:SI 2 "s_register_operand" "r,r")
(match_operand:SI 3 "arm_rhs_operand" "rM,rM")])))
! (clobber (reg:CC 24))]
"TARGET_ARM"
"#"
[(set_attr "conds" "clob")
--- 7663,7669 ----
(match_operator:SI 7 "shift_operator"
[(match_operand:SI 2 "s_register_operand" "r,r")
(match_operand:SI 3 "arm_rhs_operand" "rM,rM")])))
! (clobber (reg:CC CC_REGNUM))]
"TARGET_ARM"
"#"
[(set_attr "conds" "clob")
***************
*** 7691,7697 ****
(match_operator:SI 9 "shift_operator"
[(match_operand:SI 3 "s_register_operand" "r")
(match_operand:SI 4 "arm_rhs_operand" "rM")])))
! (clobber (reg:CC 24))]
"TARGET_ARM"
"#"
[(set_attr "conds" "clob")
--- 7700,7706 ----
(match_operator:SI 9 "shift_operator"
[(match_operand:SI 3 "s_register_operand" "r")
(match_operand:SI 4 "arm_rhs_operand" "rM")])))
! (clobber (reg:CC CC_REGNUM))]
"TARGET_ARM"
"#"
[(set_attr "conds" "clob")
***************
*** 7725,7731 ****
(match_operator:SI 7 "shiftable_operator"
[(match_operand:SI 2 "s_register_operand" "r")
(match_operand:SI 3 "arm_rhs_operand" "rI")])))
! (clobber (reg:CC 24))]
"TARGET_ARM"
"#"
[(set_attr "conds" "clob")
--- 7734,7740 ----
(match_operator:SI 7 "shiftable_operator"
[(match_operand:SI 2 "s_register_operand" "r")
(match_operand:SI 3 "arm_rhs_operand" "rI")])))
! (clobber (reg:CC CC_REGNUM))]
"TARGET_ARM"
"#"
[(set_attr "conds" "clob")
***************
*** 7757,7763 ****
[(match_operand:SI 2 "s_register_operand" "r")
(match_operand:SI 3 "arm_rhs_operand" "rI")])
(not:SI (match_operand:SI 1 "s_register_operand" "r"))))
! (clobber (reg:CC 24))]
"TARGET_ARM"
"#"
[(set_attr "conds" "clob")
--- 7766,7772 ----
[(match_operand:SI 2 "s_register_operand" "r")
(match_operand:SI 3 "arm_rhs_operand" "rI")])
(not:SI (match_operand:SI 1 "s_register_operand" "r"))))
! (clobber (reg:CC CC_REGNUM))]
"TARGET_ARM"
"#"
[(set_attr "conds" "clob")
***************
*** 7787,7793 ****
(match_operand:SI 4 "arm_add_operand" "rIL,rIL")])
(neg:SI (match_operand:SI 2 "s_register_operand" "r,r"))
(match_operand:SI 1 "arm_not_operand" "0,?rIK")))
! (clobber (reg:CC 24))]
"TARGET_ARM"
"#"
[(set_attr "conds" "clob")
--- 7796,7802 ----
(match_operand:SI 4 "arm_add_operand" "rIL,rIL")])
(neg:SI (match_operand:SI 2 "s_register_operand" "r,r"))
(match_operand:SI 1 "arm_not_operand" "0,?rIK")))
! (clobber (reg:CC CC_REGNUM))]
"TARGET_ARM"
"#"
[(set_attr "conds" "clob")
***************
*** 7818,7824 ****
(match_operand:SI 4 "arm_add_operand" "rIL,rIL")])
(match_operand:SI 1 "arm_not_operand" "0,?rIK")
(neg:SI (match_operand:SI 2 "s_register_operand" "r,r"))))
! (clobber (reg:CC 24))]
"TARGET_ARM"
"#"
[(set_attr "conds" "clob")
--- 7827,7833 ----
(match_operand:SI 4 "arm_add_operand" "rIL,rIL")])
(match_operand:SI 1 "arm_not_operand" "0,?rIK")
(neg:SI (match_operand:SI 2 "s_register_operand" "r,r"))))
! (clobber (reg:CC CC_REGNUM))]
"TARGET_ARM"
"#"
[(set_attr "conds" "clob")
***************
*** 8411,8417 ****
(define_peephole
[(set (match_operand:SI 0 "s_register_operand" "=r")
(match_operand:SI 1 "s_register_operand" "r"))
! (set (reg:CC 24)
(compare:CC (match_dup 1) (const_int 0)))]
"TARGET_ARM
"
--- 8420,8426 ----
(define_peephole
[(set (match_operand:SI 0 "s_register_operand" "=r")
(match_operand:SI 1 "s_register_operand" "r"))
! (set (reg:CC CC_REGNUM)
(compare:CC (match_dup 1) (const_int 0)))]
"TARGET_ARM
"
***************
*** 8520,8526 ****
;; extension is not needed.
(define_split
! [(set (reg:CC_Z 24)
(compare:CC_Z
(ashift:SI (subreg:SI (match_operand:QI 0 "memory_operand" "") 0)
(const_int 24))
--- 8529,8535 ----
;; extension is not needed.
(define_split
! [(set (reg:CC_Z CC_REGNUM)
(compare:CC_Z
(ashift:SI (subreg:SI (match_operand:QI 0 "memory_operand" "") 0)
(const_int 24))
***************
*** 8530,8536 ****
&& (((unsigned HOST_WIDE_INT) INTVAL (operands[1]))
== (((unsigned HOST_WIDE_INT) INTVAL (operands[1])) >> 24) << 24)"
[(set (match_dup 2) (zero_extend:SI (match_dup 0)))
! (set (reg:CC 24) (compare:CC (match_dup 2) (match_dup 1)))]
"
operands[1] = GEN_INT (((unsigned long) INTVAL (operands[1])) >> 24);
"
--- 8539,8545 ----
&& (((unsigned HOST_WIDE_INT) INTVAL (operands[1]))
== (((unsigned HOST_WIDE_INT) INTVAL (operands[1])) >> 24) << 24)"
[(set (match_dup 2) (zero_extend:SI (match_dup 0)))
! (set (reg:CC CC_REGNUM) (compare:CC (match_dup 2) (match_dup 1)))]
"
operands[1] = GEN_INT (((unsigned long) INTVAL (operands[1])) >> 24);
"
***************
*** 8625,8631 ****
[(match_operand 2 "" "") (match_operand 3 "" "")])
(match_dup 0)
(match_operand 4 "" "")))
! (clobber (reg:CC 24))]
"TARGET_ARM && reload_completed"
[(set (match_dup 5) (match_dup 6))
(cond_exec (match_dup 7)
--- 8634,8640 ----
[(match_operand 2 "" "") (match_operand 3 "" "")])
(match_dup 0)
(match_operand 4 "" "")))
! (clobber (reg:CC CC_REGNUM))]
"TARGET_ARM && reload_completed"
[(set (match_dup 5) (match_dup 6))
(cond_exec (match_dup 7)
***************
*** 8636,8642 ****
operands[2], operands[3]);
enum rtx_code rc = GET_CODE (operands[1]);
! operands[5] = gen_rtx_REG (mode, 24);
operands[6] = gen_rtx_COMPARE (mode, operands[2], operands[3]);
if (mode == CCFPmode || mode == CCFPEmode)
rc = reverse_condition_maybe_unordered (rc);
--- 8645,8651 ----
operands[2], operands[3]);
enum rtx_code rc = GET_CODE (operands[1]);
! operands[5] = gen_rtx_REG (mode, CC_REGNUM);
operands[6] = gen_rtx_COMPARE (mode, operands[2], operands[3]);
if (mode == CCFPmode || mode == CCFPEmode)
rc = reverse_condition_maybe_unordered (rc);
***************
*** 8653,8659 ****
[(match_operand 2 "" "") (match_operand 3 "" "")])
(match_operand 4 "" "")
(match_dup 0)))
! (clobber (reg:CC 24))]
"TARGET_ARM && reload_completed"
[(set (match_dup 5) (match_dup 6))
(cond_exec (match_op_dup 1 [(match_dup 5) (const_int 0)])
--- 8662,8668 ----
[(match_operand 2 "" "") (match_operand 3 "" "")])
(match_operand 4 "" "")
(match_dup 0)))
! (clobber (reg:CC CC_REGNUM))]
"TARGET_ARM && reload_completed"
[(set (match_dup 5) (match_dup 6))
(cond_exec (match_op_dup 1 [(match_dup 5) (const_int 0)])
***************
*** 8663,8669 ****
enum machine_mode mode = SELECT_CC_MODE (GET_CODE (operands[1]),
operands[2], operands[3]);
! operands[5] = gen_rtx_REG (mode, 24);
operands[6] = gen_rtx_COMPARE (mode, operands[2], operands[3]);
}"
)
--- 8672,8678 ----
enum machine_mode mode = SELECT_CC_MODE (GET_CODE (operands[1]),
operands[2], operands[3]);
! operands[5] = gen_rtx_REG (mode, CC_REGNUM);
operands[6] = gen_rtx_COMPARE (mode, operands[2], operands[3]);
}"
)
***************
*** 8674,8680 ****
[(match_operand 2 "" "") (match_operand 3 "" "")])
(match_operand 4 "" "")
(match_operand 5 "" "")))
! (clobber (reg:CC 24))]
"TARGET_ARM && reload_completed"
[(set (match_dup 6) (match_dup 7))
(cond_exec (match_op_dup 1 [(match_dup 6) (const_int 0)])
--- 8683,8689 ----
[(match_operand 2 "" "") (match_operand 3 "" "")])
(match_operand 4 "" "")
(match_operand 5 "" "")))
! (clobber (reg:CC CC_REGNUM))]
"TARGET_ARM && reload_completed"
[(set (match_dup 6) (match_dup 7))
(cond_exec (match_op_dup 1 [(match_dup 6) (const_int 0)])
***************
*** 8687,8693 ****
operands[2], operands[3]);
enum rtx_code rc = GET_CODE (operands[1]);
! operands[6] = gen_rtx_REG (mode, 24);
operands[7] = gen_rtx_COMPARE (mode, operands[2], operands[3]);
if (mode == CCFPmode || mode == CCFPEmode)
rc = reverse_condition_maybe_unordered (rc);
--- 8696,8702 ----
operands[2], operands[3]);
enum rtx_code rc = GET_CODE (operands[1]);
! operands[6] = gen_rtx_REG (mode, CC_REGNUM);
operands[7] = gen_rtx_COMPARE (mode, operands[2], operands[3]);
if (mode == CCFPmode || mode == CCFPEmode)
rc = reverse_condition_maybe_unordered (rc);
***************
*** 8704,8710 ****
[(match_operand 2 "" "") (match_operand 3 "" "")])
(match_operand 4 "" "")
(match_operand 5 "" "")))
! (clobber (reg:CC 24))]
"TARGET_ARM && reload_completed && 0"
[(set (match_dup 6) (match_dup 7))
(set (match_dup 0)
--- 8713,8719 ----
[(match_operand 2 "" "") (match_operand 3 "" "")])
(match_operand 4 "" "")
(match_operand 5 "" "")))
! (clobber (reg:CC CC_REGNUM))]
"TARGET_ARM && reload_completed && 0"
[(set (match_dup 6) (match_dup 7))
(set (match_dup 0)
***************
*** 8716,8722 ****
enum machine_mode mode = SELECT_CC_MODE (GET_CODE (operands[1]),
operands[2], operands[3]);
! operands[6] = gen_rtx_REG (mode, 24);
operands[7] = gen_rtx_COMPARE (mode, operands[2], operands[3]);
}"
)
--- 8725,8731 ----
enum machine_mode mode = SELECT_CC_MODE (GET_CODE (operands[1]),
operands[2], operands[3]);
! operands[6] = gen_rtx_REG (mode, CC_REGNUM);
operands[7] = gen_rtx_COMPARE (mode, operands[2], operands[3]);
}"
)
***************
*** 8729,8735 ****
(match_operand:SI 4 "arm_rhs_operand" "")
(not:SI
(match_operand:SI 5 "s_register_operand" ""))))
! (clobber (reg:CC 24))]
"TARGET_ARM && reload_completed"
[(set (match_dup 6) (match_dup 7))
(set (match_dup 0)
--- 8738,8744 ----
(match_operand:SI 4 "arm_rhs_operand" "")
(not:SI
(match_operand:SI 5 "s_register_operand" ""))))
! (clobber (reg:CC CC_REGNUM))]
"TARGET_ARM && reload_completed"
[(set (match_dup 6) (match_dup 7))
(set (match_dup 0)
***************
*** 8741,8747 ****
enum machine_mode mode = SELECT_CC_MODE (GET_CODE (operands[1]),
operands[2], operands[3]);
! operands[6] = gen_rtx_REG (mode, 24);
operands[7] = gen_rtx (COMPARE, mode, operands[2], operands[3]);
}"
)
--- 8750,8756 ----
enum machine_mode mode = SELECT_CC_MODE (GET_CODE (operands[1]),
operands[2], operands[3]);
! operands[6] = gen_rtx_REG (mode, CC_REGNUM);
operands[7] = gen_rtx (COMPARE, mode, operands[2], operands[3]);
}"
)