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ia64 mulhi3
- To: gcc-patches at gcc dot gnu dot org
- Subject: ia64 mulhi3
- From: Richard Henderson <rth at cygnus dot com>
- Date: Tue, 5 Sep 2000 16:18:23 -0700
For a 16-bit multiply, we needn't go to the trouble of moving
the inputs to the FPU. We've got a handy SIMD instruction that
can do it in the integer registers.
expand_binop will already use the narrower multiply if it can.
I've not yet investigated other potential code quality interactions.
It may be that we need to add addhi3 and other such patterns to avoid
extraneous sign/zero extensions with other HImode arithmetic.
r~
* config/ia64/ia64.md (mulhi3): New.
Index: ia64.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/ia64/ia64.md,v
retrieving revision 1.42
diff -c -p -d -r1.42 ia64.md
*** ia64.md 2000/09/01 22:22:54 1.42
--- ia64.md 2000/09/05 23:11:13
***************
*** 1316,1321 ****
--- 1316,1336 ----
;; ::::::::::::::::::::
;; ::
+ ;; :: 16 bit Integer arithmetic
+ ;; ::
+ ;; ::::::::::::::::::::
+
+ (define_insn "mulhi3"
+ [(set (match_operand:HI 0 "gr_register_operand" "=r")
+ (mult:HI (match_operand:HI 1 "gr_register_operand" "r")
+ (match_operand:HI 2 "gr_register_operand" "r")))]
+ ""
+ "pmpy.r %0 = %1, %2"
+ [(set_attr "type" "I")])
+
+
+ ;; ::::::::::::::::::::
+ ;; ::
;; :: 32 bit Integer arithmetic
;; ::
;; ::::::::::::::::::::