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Re: gcc intrinsics for am33 parallel integer arithmetic
- To: gcc-patches at gcc dot gnu dot org
- Subject: Re: gcc intrinsics for am33 parallel integer arithmetic
- From: Matthew Hiller <hiller at cygnus dot com>
- Date: Thu, 31 Aug 2000 12:16:47 -0700 (PDT)
The am33 has a set of parallel integer arithmetic instructions
that execute two integer arithmetic operations simultaneously. This patch
implements 36 of them as intrinsics. Binutils already supports these
instructions.
This version of the patch should resolve all the problems that
were found in the first version of the patch.
2000-08-31 Matthew Hiller <hiller@cygnus.com>
* config/mn10300/dsp.h: New file.
(__ADD_ADD, __ADD_SUB, etc): Prototypes for intrinsics.
* config/mn10300/mn10300-protos.h (am33_init_builtins)
(am33_expand_builtin): New prototypes.
* config/mn10300/mn10300.c (def_builtin): New macro.
(bdesc_void4arg): Static struct containing descriptions of new
intrinsics as builtins.
(am33_init_builtins): New function.
(am33_expand_dsp_builtin): New function.
(am33_expand_builtin): New function.
* config/mn10300/mn10300.h (am33_builtins): New enum.
(MD_INIT_BUILTINS): New macro.
(MD_EXPAND_BUILTIN): New macro.
* config/mn10300/mn10300.md (add_add, add_sub, etc.): New patterns
added that correspond to the new intrinsics.
* config/mn10300/t-mn10300 (EXTRA_HEADERS): Defined to include
dsp.h.
Index: dsp.h
===================================================================
diff -c -3 -p /dev/null dsp.h
*** /dev/null Tue May 5 13:32:27 1998
--- dsp.h Mon Aug 28 13:55:47 2000
***************
*** 0 ****
--- 1,42 ----
+ #ifndef __DSP_H__
+ #define __DSP_H__
+
+ /* Multiple arithmetic instructions */
+ void __ADD_ADD PARAMS ((long rm1, long rn1, long rm2, long rn2));
+ void __ADD_SUB PARAMS ((long rm1, long rn1, long rm2, long rn2));
+ void __ADD_MOV PARAMS ((long rm1, long rn1, long rm2, long rn2));
+ void __ADD_ASR PARAMS ((long rm1, long rn1, long rm2, long rn2));
+ void __ADD_LSR PARAMS ((long rm1, long rn1, long rm2, long rn2));
+ void __ADD_ASL PARAMS ((long rm1, long rn1, long rm2, long rn2));
+ void __SUB_ADD PARAMS ((long rm1, long rn1, long rm2, long rn2));
+ void __SUB_SUB PARAMS ((long rm1, long rn1, long rm2, long rn2));
+ void __SUB_MOV PARAMS ((long rm1, long rn1, long rm2, long rn2));
+ void __SUB_ASR PARAMS ((long rm1, long rn1, long rm2, long rn2));
+ void __SUB_LSR PARAMS ((long rm1, long rn1, long rm2, long rn2));
+ void __SUB_ASL PARAMS ((long rm1, long rn1, long rm2, long rn2));
+ void __MOV_ADD PARAMS ((long rm1, long rn1, long rm2, long rn2));
+ void __MOV_SUB PARAMS ((long rm1, long rn1, long rm2, long rn2));
+ void __MOV_MOV PARAMS ((long rm1, long rn1, long rm2, long rn2));
+ void __MOV_ASR PARAMS ((long rm1, long rn1, long rm2, long rn2));
+ void __MOV_LSR PARAMS ((long rm1, long rn1, long rm2, long rn2));
+ void __MOV_ASL PARAMS ((long rm1, long rn1, long rm2, long rn2));
+ void __AND_ADD PARAMS ((long rm1, long rn1, long rm2, long rn2));
+ void __AND_SUB PARAMS ((long rm1, long rn1, long rm2, long rn2));
+ void __AND_MOV PARAMS ((long rm1, long rn1, long rm2, long rn2));
+ void __AND_ASR PARAMS ((long rm1, long rn1, long rm2, long rn2));
+ void __AND_LSR PARAMS ((long rm1, long rn1, long rm2, long rn2));
+ void __AND_ASL PARAMS ((long rm1, long rn1, long rm2, long rn2));
+ void __OR_ADD PARAMS ((long rm1, long rn1, long rm2, long rn2));
+ void __OR_SUB PARAMS ((long rm1, long rn1, long rm2, long rn2));
+ void __OR_MOV PARAMS ((long rm1, long rn1, long rm2, long rn2));
+ void __OR_ASR PARAMS ((long rm1, long rn1, long rm2, long rn2));
+ void __OR_LSR PARAMS ((long rm1, long rn1, long rm2, long rn2));
+ void __OR_ASL PARAMS ((long rm1, long rn1, long rm2, long rn2));
+ void __XOR_ADD PARAMS ((long rm1, long rn1, long rm2, long rn2));
+ void __XOR_SUB PARAMS ((long rm1, long rn1, long rm2, long rn2));
+ void __XOR_MOV PARAMS ((long rm1, long rn1, long rm2, long rn2));
+ void __XOR_ASR PARAMS ((long rm1, long rn1, long rm2, long rn2));
+ void __XOR_LSR PARAMS ((long rm1, long rn1, long rm2, long rn2));
+ void __XOR_ASL PARAMS ((long rm1, long rn1, long rm2, long rn2));
+
+ #endif
Index: mn10300-protos.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/mn10300/mn10300-protos.h,v
retrieving revision 1.2
diff -c -3 -p -r1.2 mn10300-protos.h
*** mn10300-protos.h 2000/04/21 21:19:55 1.2
--- mn10300-protos.h 2000/08/31 19:02:58
*************** extern struct rtx_def *function_arg PARA
*** 46,51 ****
--- 46,55 ----
extern int function_arg_partial_nregs PARAMS ((CUMULATIVE_ARGS *,
enum machine_mode, tree, int));
extern struct rtx_def *mn10300_va_arg PARAMS ((tree, tree));
+ #ifdef RTX_CODE
+ extern rtx am33_expand_builtin PARAMS ((tree, rtx, rtx, enum machine_mode, int));
+ #endif
+
#endif /* TREE_CODE */
extern struct rtx_def *mn10300_builtin_saveregs PARAMS ((void));
*************** extern int initial_offset PARAMS ((int,
*** 56,58 ****
--- 60,63 ----
extern int can_use_return_insn PARAMS ((void));
extern int mask_ok_for_mem_btst PARAMS ((int, int));
+ extern void am33_init_builtins PARAMS ((void));
Index: mn10300.c
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/mn10300/mn10300.c,v
retrieving revision 1.29
diff -c -3 -p -r1.29 mn10300.c
*** mn10300.c 2000/05/20 23:05:58 1.29
--- mn10300.c 2000/08/31 19:02:58
*************** mn10300_address_cost (x, unsig)
*** 1115,1117 ****
--- 1115,1324 ----
}
}
+
+
+ #define def_builtin(name, type, code) \
+ builtin_function ((name), (type), (code), BUILT_IN_MD, NULL_PTR)
+
+ struct builtin_description
+ {
+ enum insn_code icode;
+ const char *name;
+ enum am33_builtins code;
+ enum rtx_code comparison;
+ unsigned int flag;
+ };
+
+ static struct builtin_description bdesc_void4arg[] =
+ {
+ { CODE_FOR_add_add, "__ADD_ADD", AM33_BUILTIN_ADD_ADD, 0, 0 },
+ { CODE_FOR_add_sub, "__ADD_SUB", AM33_BUILTIN_ADD_SUB, 0, 0 },
+ { CODE_FOR_add_mov, "__ADD_MOV", AM33_BUILTIN_ADD_MOV, 0, 0 },
+ { CODE_FOR_add_asr, "__ADD_ASR", AM33_BUILTIN_ADD_ASR, 0, 0 },
+ { CODE_FOR_add_lsr, "__ADD_LSR", AM33_BUILTIN_ADD_LSR, 0, 0 },
+ { CODE_FOR_add_asl, "__ADD_ASL", AM33_BUILTIN_ADD_ASL, 0, 0 },
+ { CODE_FOR_sub_add, "__SUB_ADD", AM33_BUILTIN_SUB_ADD, 0, 0 },
+ { CODE_FOR_sub_sub, "__SUB_SUB", AM33_BUILTIN_SUB_SUB, 0, 0 },
+ { CODE_FOR_sub_mov, "__SUB_MOV", AM33_BUILTIN_SUB_MOV, 0, 0 },
+ { CODE_FOR_sub_asr, "__SUB_ASR", AM33_BUILTIN_SUB_ASR, 0, 0 },
+ { CODE_FOR_sub_lsr, "__SUB_LSR", AM33_BUILTIN_SUB_LSR, 0, 0 },
+ { CODE_FOR_sub_asl, "__SUB_ASL", AM33_BUILTIN_SUB_ASL, 0, 0 },
+ { CODE_FOR_mov_add, "__MOV_ADD", AM33_BUILTIN_MOV_ADD, 0, 0 },
+ { CODE_FOR_mov_sub, "__MOV_SUB", AM33_BUILTIN_MOV_SUB, 0, 0 },
+ { CODE_FOR_mov_mov, "__MOV_MOV", AM33_BUILTIN_MOV_MOV, 0, 0 },
+ { CODE_FOR_mov_asr, "__MOV_ASR", AM33_BUILTIN_MOV_ASR, 0, 0 },
+ { CODE_FOR_mov_lsr, "__MOV_LSR", AM33_BUILTIN_MOV_LSR, 0, 0 },
+ { CODE_FOR_mov_asl, "__MOV_ASL", AM33_BUILTIN_MOV_ASL, 0, 0 },
+ { CODE_FOR_and_add, "__AND_ADD", AM33_BUILTIN_AND_ADD, 0, 0 },
+ { CODE_FOR_and_sub, "__AND_SUB", AM33_BUILTIN_AND_SUB, 0, 0 },
+ { CODE_FOR_and_mov, "__AND_MOV", AM33_BUILTIN_AND_MOV, 0, 0 },
+ { CODE_FOR_and_asr, "__AND_ASR", AM33_BUILTIN_AND_ASR, 0, 0 },
+ { CODE_FOR_and_lsr, "__AND_LSR", AM33_BUILTIN_AND_LSR, 0, 0 },
+ { CODE_FOR_and_asl, "__AND_ASL", AM33_BUILTIN_AND_ASL, 0, 0 },
+ { CODE_FOR_or_add, "__OR_ADD", AM33_BUILTIN_OR_ADD, 0, 0 },
+ { CODE_FOR_or_sub, "__OR_SUB", AM33_BUILTIN_OR_SUB, 0, 0 },
+ { CODE_FOR_or_mov, "__OR_MOV", AM33_BUILTIN_OR_MOV, 0, 0 },
+ { CODE_FOR_or_asr, "__OR_ASR", AM33_BUILTIN_OR_ASR, 0, 0 },
+ { CODE_FOR_or_lsr, "__OR_LSR", AM33_BUILTIN_OR_LSR, 0, 0 },
+ { CODE_FOR_or_asl, "__OR_ASL", AM33_BUILTIN_OR_ASL, 0, 0 },
+ { CODE_FOR_xor_add, "__XOR_ADD", AM33_BUILTIN_XOR_ADD, 0, 0 },
+ { CODE_FOR_xor_sub, "__XOR_SUB", AM33_BUILTIN_XOR_SUB, 0, 0 },
+ { CODE_FOR_xor_mov, "__XOR_MOV", AM33_BUILTIN_XOR_MOV, 0, 0 },
+ { CODE_FOR_xor_asr, "__XOR_ASR", AM33_BUILTIN_XOR_ASR, 0, 0 },
+ { CODE_FOR_xor_lsr, "__XOR_LSR", AM33_BUILTIN_XOR_LSR, 0, 0 },
+ { CODE_FOR_xor_asl, "__XOR_ASL", AM33_BUILTIN_XOR_ASL, 0, 0 }
+ };
+
+ void
+ am33_init_builtins ()
+ {
+ if (TARGET_AM33)
+ {
+ tree endlink = tree_cons (NULL_TREE, void_type_node, NULL_TREE);
+
+ tree void_ftype_ssi_ssi_ssi_ssi
+ = build_function_type (void_type_node,
+ tree_cons (NULL_TREE, integer_type_node,
+ tree_cons (NULL_TREE, integer_type_node,
+ tree_cons (NULL_TREE, integer_type_node,
+ tree_cons (NULL_TREE, integer_type_node,
+ endlink)))));
+ def_builtin ("__ADD_ADD", void_ftype_ssi_ssi_ssi_ssi,
+ AM33_BUILTIN_ADD_ADD);
+ def_builtin ("__ADD_SUB", void_ftype_ssi_ssi_ssi_ssi,
+ AM33_BUILTIN_ADD_SUB);
+ def_builtin ("__ADD_MOV", void_ftype_ssi_ssi_ssi_ssi,
+ AM33_BUILTIN_ADD_MOV);
+ def_builtin ("__ADD_ASR", void_ftype_ssi_ssi_ssi_ssi,
+ AM33_BUILTIN_ADD_ASR);
+ def_builtin ("__ADD_LSR", void_ftype_ssi_ssi_ssi_ssi,
+ AM33_BUILTIN_ADD_LSR);
+ def_builtin ("__ADD_ASL", void_ftype_ssi_ssi_ssi_ssi,
+ AM33_BUILTIN_ADD_ASL);
+ def_builtin ("__SUB_ADD", void_ftype_ssi_ssi_ssi_ssi,
+ AM33_BUILTIN_SUB_ADD);
+ def_builtin ("__SUB_SUB", void_ftype_ssi_ssi_ssi_ssi,
+ AM33_BUILTIN_SUB_SUB);
+ def_builtin ("__SUB_MOV", void_ftype_ssi_ssi_ssi_ssi,
+ AM33_BUILTIN_SUB_MOV);
+ def_builtin ("__SUB_ASR", void_ftype_ssi_ssi_ssi_ssi,
+ AM33_BUILTIN_SUB_ASR);
+ def_builtin ("__SUB_LSR", void_ftype_ssi_ssi_ssi_ssi,
+ AM33_BUILTIN_SUB_LSR);
+ def_builtin ("__SUB_ASL", void_ftype_ssi_ssi_ssi_ssi,
+ AM33_BUILTIN_SUB_ASL);
+ def_builtin ("__MOV_ADD", void_ftype_ssi_ssi_ssi_ssi,
+ AM33_BUILTIN_MOV_ADD);
+ def_builtin ("__MOV_SUB", void_ftype_ssi_ssi_ssi_ssi,
+ AM33_BUILTIN_MOV_SUB);
+ def_builtin ("__MOV_MOV", void_ftype_ssi_ssi_ssi_ssi,
+ AM33_BUILTIN_MOV_MOV);
+ def_builtin ("__MOV_ASR", void_ftype_ssi_ssi_ssi_ssi,
+ AM33_BUILTIN_MOV_ASR);
+ def_builtin ("__MOV_LSR", void_ftype_ssi_ssi_ssi_ssi,
+ AM33_BUILTIN_MOV_LSR);
+ def_builtin ("__MOV_ASL", void_ftype_ssi_ssi_ssi_ssi,
+ AM33_BUILTIN_MOV_ASL);
+ def_builtin ("__AND_ADD", void_ftype_ssi_ssi_ssi_ssi,
+ AM33_BUILTIN_AND_ADD);
+ def_builtin ("__AND_SUB", void_ftype_ssi_ssi_ssi_ssi,
+ AM33_BUILTIN_AND_SUB);
+ def_builtin ("__AND_MOV", void_ftype_ssi_ssi_ssi_ssi,
+ AM33_BUILTIN_AND_MOV);
+ def_builtin ("__AND_ASR", void_ftype_ssi_ssi_ssi_ssi,
+ AM33_BUILTIN_AND_ASR);
+ def_builtin ("__AND_LSR", void_ftype_ssi_ssi_ssi_ssi,
+ AM33_BUILTIN_AND_LSR);
+ def_builtin ("__AND_ASL", void_ftype_ssi_ssi_ssi_ssi,
+ AM33_BUILTIN_AND_ASL);
+ def_builtin ("__OR_ADD", void_ftype_ssi_ssi_ssi_ssi,
+ AM33_BUILTIN_OR_ADD);
+ def_builtin ("__OR_SUB", void_ftype_ssi_ssi_ssi_ssi,
+ AM33_BUILTIN_OR_SUB);
+ def_builtin ("__OR_MOV", void_ftype_ssi_ssi_ssi_ssi,
+ AM33_BUILTIN_OR_MOV);
+ def_builtin ("__OR_ASR", void_ftype_ssi_ssi_ssi_ssi,
+ AM33_BUILTIN_OR_ASR);
+ def_builtin ("__OR_LSR", void_ftype_ssi_ssi_ssi_ssi,
+ AM33_BUILTIN_OR_LSR);
+ def_builtin ("__OR_ASL", void_ftype_ssi_ssi_ssi_ssi,
+ AM33_BUILTIN_OR_ASL);
+ def_builtin ("__XOR_ADD", void_ftype_ssi_ssi_ssi_ssi,
+ AM33_BUILTIN_XOR_ADD);
+ def_builtin ("__XOR_SUB", void_ftype_ssi_ssi_ssi_ssi,
+ AM33_BUILTIN_XOR_SUB);
+ def_builtin ("__XOR_MOV", void_ftype_ssi_ssi_ssi_ssi,
+ AM33_BUILTIN_XOR_MOV);
+ def_builtin ("__XOR_ASR", void_ftype_ssi_ssi_ssi_ssi,
+ AM33_BUILTIN_XOR_ASR);
+ def_builtin ("__XOR_LSR", void_ftype_ssi_ssi_ssi_ssi,
+ AM33_BUILTIN_XOR_LSR);
+ def_builtin ("__XOR_ASL", void_ftype_ssi_ssi_ssi_ssi,
+ AM33_BUILTIN_XOR_ASL);
+ }
+ }
+
+ static rtx
+ am33_expand_dsp_builtin (icode, arglist)
+ enum insn_code icode;
+ tree arglist;
+ {
+ rtx pat;
+ tree arg0 = TREE_VALUE (arglist);
+ tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
+ tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
+ tree arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist))));
+ rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
+ rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
+ rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
+ rtx op3 = expand_expr (arg3, NULL_RTX, VOIDmode, 0);
+ enum machine_mode mode0 = insn_data[icode].operand[0].mode;
+ enum machine_mode mode1 = insn_data[icode].operand[1].mode;
+ enum machine_mode mode2 = insn_data[icode].operand[2].mode;
+ enum machine_mode mode3 = insn_data[icode].operand[3].mode;
+ int operand_type_error;
+
+ if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
+ error ("operand 0 of dsp intrinsic of unsuitable type");
+ if (!lvalue_p (arg1))
+ error ("operand 1 of dsp intrinsic not an lvalue");
+ if (! (*insn_data[icode].operand[2].predicate) (op2, mode2))
+ error ("operand 2 of dsp intrinsic of unsuitable type");
+ if (!lvalue_p (arg3))
+ error ("operand 3 of dsp intrinsic not an lvalue");
+ if (REG_P (op1) && REG_P (op3) && REGNO (op1) == REGNO (op3))
+ error ("operands 1 and 3 of dsp intrinsic are the same");
+
+ pat = GEN_FCN (icode) (op0, op0, op1, op2, op2, op3);
+ if (! pat)
+ return 0;
+ emit_insn (pat);
+
+ return 0;
+
+ }
+
+ rtx
+ am33_expand_builtin (exp, target, subtarget, mode, ignore)
+ tree exp;
+ rtx target ATTRIBUTE_UNUSED;
+ rtx subtarget ATTRIBUTE_UNUSED;
+ enum machine_mode mode ATTRIBUTE_UNUSED;
+ int ignore ATTRIBUTE_UNUSED;
+ {
+ tree arglist = TREE_OPERAND (exp, 1);
+ tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
+ unsigned fcode = (unsigned)DECL_FUNCTION_CODE (fndecl);
+ unsigned i;
+ struct builtin_description *d;
+
+ if (TARGET_AM33)
+ {
+ for (i = 0, d = bdesc_void4arg; i < sizeof (bdesc_void4arg) / sizeof *d;
+ i++, d++)
+ if (d->code == fcode)
+ return am33_expand_dsp_builtin (d->icode, arglist);
+ return 0;
+ }
+ return 0;
+ }
Index: mn10300.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/mn10300/mn10300.h,v
retrieving revision 1.40
diff -c -3 -p -r1.40 mn10300.h
*** mn10300.h 2000/08/26 21:47:21 1.40
--- mn10300.h 2000/08/31 19:02:58
*************** do { char dstr[30]; \
*** 1123,1125 ****
--- 1123,1174 ----
#define FILE_ASM_OP "\t.file\n"
+ enum am33_builtins
+ {
+ AM33_BUILTIN_ADD_ADD,
+ AM33_BUILTIN_ADD_SUB,
+ AM33_BUILTIN_ADD_MOV,
+ AM33_BUILTIN_ADD_ASR,
+ AM33_BUILTIN_ADD_LSR,
+ AM33_BUILTIN_ADD_ASL,
+ AM33_BUILTIN_SUB_ADD,
+ AM33_BUILTIN_SUB_SUB,
+ AM33_BUILTIN_SUB_MOV,
+ AM33_BUILTIN_SUB_ASR,
+ AM33_BUILTIN_SUB_LSR,
+ AM33_BUILTIN_SUB_ASL,
+ AM33_BUILTIN_MOV_ADD,
+ AM33_BUILTIN_MOV_SUB,
+ AM33_BUILTIN_MOV_MOV,
+ AM33_BUILTIN_MOV_ASR,
+ AM33_BUILTIN_MOV_LSR,
+ AM33_BUILTIN_MOV_ASL,
+ AM33_BUILTIN_AND_ADD,
+ AM33_BUILTIN_AND_SUB,
+ AM33_BUILTIN_AND_MOV,
+ AM33_BUILTIN_AND_ASR,
+ AM33_BUILTIN_AND_LSR,
+ AM33_BUILTIN_AND_ASL,
+ AM33_BUILTIN_OR_ADD,
+ AM33_BUILTIN_OR_SUB,
+ AM33_BUILTIN_OR_MOV,
+ AM33_BUILTIN_OR_ASR,
+ AM33_BUILTIN_OR_LSR,
+ AM33_BUILTIN_OR_ASL,
+ AM33_BUILTIN_XOR_ADD,
+ AM33_BUILTIN_XOR_SUB,
+ AM33_BUILTIN_XOR_MOV,
+ AM33_BUILTIN_XOR_ASR,
+ AM33_BUILTIN_XOR_LSR,
+ AM33_BUILTIN_XOR_ASL
+ };
+
+ #define MD_INIT_BUILTINS \
+ do \
+ { \
+ am33_init_builtins (); \
+ } \
+ while (0)
+
+ #define MD_EXPAND_BUILTIN(EXP, TARGET, SUBTARGET, MODE, IGNORE) \
+ am33_expand_builtin ((EXP), (TARGET), (SUBTARGET), (MODE), (IGNORE))
Index: mn10300.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/mn10300/mn10300.md,v
retrieving revision 1.36
diff -c -3 -p -r1.36 mn10300.md
*** mn10300.md 2000/08/07 11:28:02 1.36
--- mn10300.md 2000/08/31 19:02:58
***************
*** 2165,2167 ****
--- 2165,2561 ----
"add %0,%0\;bcc %1"
[(set_attr "cc" "clobber")])
+
+ ;; ----------------------------------------------------------------------
+ ;; am33 intrinsics
+ ;; ----------------------------------------------------------------------
+
+ ;; Since combine will not attempt to assemble parallels like what are
+ ;; shown below, there's no need to put unspec's in the patterns
+ ;; Moreover, should combine be extended to deal with non-related parallel
+ ;; instructions like what appear below, no extra work will be needed
+ ;; to get the compiler to generate DSP integer instructions automatically
+
+ (define_insn "add_add"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=&dax")
+ (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
+ (match_operand:SI 2 "general_operand" "idax")))
+ (set (match_operand:SI 3 "nonimmediate_operand" "=&dax")
+ (plus:SI (match_operand:SI 4 "nonimmediate_operand" "3")
+ (match_operand:SI 5 "general_operand" "idax")))]
+ "TARGET_AM33"
+ "add_add %2,%0,%5,%3"
+ [(set_attr "cc" "none")])
+
+ (define_insn "add_sub"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=&dax")
+ (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
+ (match_operand:SI 2 "general_operand" "idax")))
+ (set (match_operand:SI 3 "nonimmediate_operand" "=&dax")
+ (minus:SI (match_operand:SI 4 "nonimmediate_operand" "3")
+ (match_operand:SI 5 "general_operand" "idax")))]
+ "TARGET_AM33"
+ "add_sub %2,%0,%5,%3"
+ [(set_attr "cc" "none")])
+
+ (define_insn "add_mov"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=&dax")
+ (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
+ (match_operand:SI 2 "general_operand" "idax")))
+ (set (match_operand:SI 3 "nonimmediate_operand" "=&dax")
+ (match_operand:SI 5 "general_operand" "idax"))]
+ "TARGET_AM33"
+ "add_mov %2,%0,%5,%3"
+ [(set_attr "cc" "none")])
+
+ (define_insn "add_asr"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=&dax")
+ (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
+ (match_operand:SI 2 "general_operand" "idax")))
+ (set (match_operand:SI 3 "nonimmediate_operand" "=&dax")
+ (ashiftrt:SI (match_operand:SI 4 "nonimmediate_operand" "3")
+ (match_operand:SI 5 "general_operand" "idax")))]
+ "TARGET_AM33"
+ "add_asr %2,%0,%5,%3"
+ [(set_attr "cc" "none")])
+
+ (define_insn "add_lsr"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=&dax")
+ (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
+ (match_operand:SI 2 "general_operand" "idax")))
+ (set (match_operand:SI 3 "nonimmediate_operand" "=&dax")
+ (lshiftrt:SI (match_operand:SI 4 "nonimmediate_operand" "3")
+ (match_operand:SI 5 "general_operand" "idax")))]
+ "TARGET_AM33"
+ "add_lsr %2,%0,%5,%3"
+ [(set_attr "cc" "none")])
+
+ (define_insn "add_asl"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=&dax")
+ (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
+ (match_operand:SI 2 "general_operand" "idax")))
+ (set (match_operand:SI 3 "nonimmediate_operand" "=&dax")
+ (ashift:SI (match_operand:SI 4 "nonimmediate_operand" "3")
+ (match_operand:SI 5 "general_operand" "idax")))]
+ "TARGET_AM33"
+ "add_asl %2,%0,%5,%3"
+ [(set_attr "cc" "none")])
+
+ (define_insn "sub_add"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=&dax")
+ (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
+ (match_operand:SI 2 "general_operand" "idax")))
+ (set (match_operand:SI 3 "nonimmediate_operand" "=&dax")
+ (plus:SI (match_operand:SI 4 "nonimmediate_operand" "3")
+ (match_operand:SI 5 "general_operand" "idax")))]
+ "TARGET_AM33"
+ "sub_add %2,%0,%5,%3"
+ [(set_attr "cc" "none")])
+
+ (define_insn "sub_sub"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=&dax")
+ (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
+ (match_operand:SI 2 "general_operand" "idax")))
+ (set (match_operand:SI 3 "nonimmediate_operand" "=&dax")
+ (minus:SI (match_operand:SI 4 "nonimmediate_operand" "3")
+ (match_operand:SI 5 "general_operand" "idax")))]
+ "TARGET_AM33"
+ "sub_sub %2,%0,%5,%3"
+ [(set_attr "cc" "none")])
+
+ (define_insn "sub_mov"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=&dax")
+ (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
+ (match_operand:SI 2 "general_operand" "idax")))
+ (set (match_operand:SI 3 "nonimmediate_operand" "=&dax")
+ (match_operand:SI 5 "general_operand" "idax"))]
+ "TARGET_AM33"
+ "sub_mov %2,%0,%5,%3"
+ [(set_attr "cc" "none")])
+
+ (define_insn "sub_asr"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=&dax")
+ (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
+ (match_operand:SI 2 "general_operand" "idax")))
+ (set (match_operand:SI 3 "nonimmediate_operand" "=&dax")
+ (ashiftrt:SI (match_operand:SI 4 "nonimmediate_operand" "3")
+ (match_operand:SI 5 "general_operand" "idax")))]
+ "TARGET_AM33"
+ "sub_asr %2,%0,%5,%3"
+ [(set_attr "cc" "none")])
+
+ (define_insn "sub_lsr"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=&dax")
+ (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
+ (match_operand:SI 2 "general_operand" "idax")))
+ (set (match_operand:SI 3 "nonimmediate_operand" "=&dax")
+ (lshiftrt:SI (match_operand:SI 4 "nonimmediate_operand" "3")
+ (match_operand:SI 5 "general_operand" "idax")))]
+ "TARGET_AM33"
+ "sub_lsr %2,%0,%5,%3"
+ [(set_attr "cc" "none")])
+
+ (define_insn "sub_asl"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=&dax")
+ (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
+ (match_operand:SI 2 "general_operand" "idax")))
+ (set (match_operand:SI 3 "nonimmediate_operand" "=&dax")
+ (ashift:SI (match_operand:SI 4 "nonimmediate_operand" "3")
+ (match_operand:SI 5 "general_operand" "idax")))]
+ "TARGET_AM33"
+ "sub_asl %2,%0,%5,%3"
+ [(set_attr "cc" "none")])
+
+ (define_insn "mov_add"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=&dax")
+ (match_operand:SI 2 "general_operand" "idax"))
+ (set (match_operand:SI 3 "nonimmediate_operand" "=&dax")
+ (plus:SI (match_operand:SI 4 "nonimmediate_operand" "3")
+ (match_operand:SI 5 "general_operand" "idax")))]
+ "TARGET_AM33"
+ "mov_add %2,%0,%5,%3"
+ [(set_attr "cc" "none")])
+
+ (define_insn "mov_sub"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=&dax")
+ (match_operand:SI 2 "general_operand" "idax"))
+ (set (match_operand:SI 3 "nonimmediate_operand" "=&dax")
+ (minus:SI (match_operand:SI 4 "nonimmediate_operand" "3")
+ (match_operand:SI 5 "general_operand" "idax")))]
+ "TARGET_AM33"
+ "mov_sub %2,%0,%5,%3"
+ [(set_attr "cc" "none")])
+
+ (define_insn "mov_mov"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=&dax")
+ (match_operand:SI 2 "general_operand" "idax"))
+ (set (match_operand:SI 3 "nonimmediate_operand" "=&dax")
+ (match_operand:SI 5 "general_operand" "idax"))]
+ "TARGET_AM33"
+ "mov_mov %2,%0,%5,%3"
+ [(set_attr "cc" "none")])
+
+ (define_insn "mov_asr"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=&dax")
+ (match_operand:SI 2 "general_operand" "idax"))
+ (set (match_operand:SI 3 "nonimmediate_operand" "=&dax")
+ (ashiftrt:SI (match_operand:SI 4 "nonimmediate_operand" "3")
+ (match_operand:SI 5 "general_operand" "idax")))]
+ "TARGET_AM33"
+ "mov_asr %2,%0,%5,%3"
+ [(set_attr "cc" "none")])
+
+ (define_insn "mov_lsr"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=&dax")
+ (match_operand:SI 2 "general_operand" "idax"))
+ (set (match_operand:SI 3 "nonimmediate_operand" "=&dax")
+ (lshiftrt:SI (match_operand:SI 4 "nonimmediate_operand" "3")
+ (match_operand:SI 5 "general_operand" "idax")))]
+ "TARGET_AM33"
+ "mov_lsr %2,%0,%5,%3"
+ [(set_attr "cc" "none")])
+
+ (define_insn "mov_asl"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=&dax")
+ (match_operand:SI 2 "general_operand" "idax"))
+ (set (match_operand:SI 3 "nonimmediate_operand" "=&dax")
+ (ashift:SI (match_operand:SI 4 "nonimmediate_operand" "3")
+ (match_operand:SI 5 "general_operand" "idax")))]
+ "TARGET_AM33"
+ "mov_asl %2,%0,%5,%3"
+ [(set_attr "cc" "none")])
+
+ (define_insn "and_add"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=&dax")
+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "0")
+ (match_operand:SI 2 "general_operand" "idax")))
+ (set (match_operand:SI 3 "nonimmediate_operand" "=&dax")
+ (plus:SI (match_operand:SI 4 "nonimmediate_operand" "3")
+ (match_operand:SI 5 "general_operand" "idax")))]
+ "TARGET_AM33"
+ "and_add %2,%0,%5,%3"
+ [(set_attr "cc" "none")])
+
+ (define_insn "and_sub"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=&dax")
+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "0")
+ (match_operand:SI 2 "general_operand" "idax")))
+ (set (match_operand:SI 3 "nonimmediate_operand" "=&dax")
+ (minus:SI (match_operand:SI 4 "nonimmediate_operand" "3")
+ (match_operand:SI 5 "general_operand" "idax")))]
+ "TARGET_AM33"
+ "and_sub %2,%0,%5,%3"
+ [(set_attr "cc" "none")])
+
+ (define_insn "and_mov"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=&dax")
+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "0")
+ (match_operand:SI 2 "general_operand" "idax")))
+ (set (match_operand:SI 3 "nonimmediate_operand" "=&dax")
+ (match_operand:SI 5 "general_operand" "idax"))]
+ "TARGET_AM33"
+ "and_mov %2,%0,%5,%3"
+ [(set_attr "cc" "none")])
+
+ (define_insn "and_asr"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=&dax")
+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "0")
+ (match_operand:SI 2 "general_operand" "idax")))
+ (set (match_operand:SI 3 "nonimmediate_operand" "=&dax")
+ (ashiftrt:SI (match_operand:SI 4 "nonimmediate_operand" "3")
+ (match_operand:SI 5 "general_operand" "idax")))]
+ "TARGET_AM33"
+ "and_asr %2,%0,%5,%3"
+ [(set_attr "cc" "none")])
+
+ (define_insn "and_lsr"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=&dax")
+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "0")
+ (match_operand:SI 2 "general_operand" "idax")))
+ (set (match_operand:SI 3 "nonimmediate_operand" "=&dax")
+ (lshiftrt:SI (match_operand:SI 4 "nonimmediate_operand" "3")
+ (match_operand:SI 5 "general_operand" "idax")))]
+ "TARGET_AM33"
+ "and_lsr %2,%0,%5,%3"
+ [(set_attr "cc" "none")])
+
+ (define_insn "and_asl"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=&dax")
+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "0")
+ (match_operand:SI 2 "general_operand" "idax")))
+ (set (match_operand:SI 3 "nonimmediate_operand" "=&dax")
+ (ashift:SI (match_operand:SI 4 "nonimmediate_operand" "3")
+ (match_operand:SI 5 "general_operand" "idax")))]
+ "TARGET_AM33"
+ "and_asl %2,%0,%5,%3"
+ [(set_attr "cc" "none")])
+
+ (define_insn "or_add"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=&dax")
+ (ior:SI (match_operand:SI 1 "nonimmediate_operand" "0")
+ (match_operand:SI 2 "general_operand" "idax")))
+ (set (match_operand:SI 3 "nonimmediate_operand" "=&dax")
+ (plus:SI (match_operand:SI 4 "nonimmediate_operand" "3")
+ (match_operand:SI 5 "general_operand" "idax")))]
+ "TARGET_AM33"
+ "or_add %2,%0,%5,%3"
+ [(set_attr "cc" "none")])
+
+ (define_insn "or_sub"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=&dax")
+ (ior:SI (match_operand:SI 1 "nonimmediate_operand" "0")
+ (match_operand:SI 2 "general_operand" "idax")))
+ (set (match_operand:SI 3 "nonimmediate_operand" "=&dax")
+ (minus:SI (match_operand:SI 4 "nonimmediate_operand" "3")
+ (match_operand:SI 5 "general_operand" "idax")))]
+ "TARGET_AM33"
+ "or_sub %2,%0,%5,%3"
+ [(set_attr "cc" "none")])
+
+ (define_insn "or_mov"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=&dax")
+ (ior:SI (match_operand:SI 1 "nonimmediate_operand" "0")
+ (match_operand:SI 2 "general_operand" "idax")))
+ (set (match_operand:SI 3 "nonimmediate_operand" "=&dax")
+ (match_operand:SI 5 "general_operand" "idax"))]
+ "TARGET_AM33"
+ "or_mov %2,%0,%5,%3"
+ [(set_attr "cc" "none")])
+
+ (define_insn "or_asr"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=&dax")
+ (ior:SI (match_operand:SI 1 "nonimmediate_operand" "0")
+ (match_operand:SI 2 "general_operand" "idax")))
+ (set (match_operand:SI 3 "nonimmediate_operand" "=&dax")
+ (ashiftrt:SI (match_operand:SI 4 "nonimmediate_operand" "3")
+ (match_operand:SI 5 "general_operand" "idax")))]
+ "TARGET_AM33"
+ "or_asr %2,%0,%5,%3"
+ [(set_attr "cc" "none")])
+
+ (define_insn "or_lsr"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=&dax")
+ (ior:SI (match_operand:SI 1 "nonimmediate_operand" "0")
+ (match_operand:SI 2 "general_operand" "idax")))
+ (set (match_operand:SI 3 "nonimmediate_operand" "=&dax")
+ (lshiftrt:SI (match_operand:SI 4 "nonimmediate_operand" "3")
+ (match_operand:SI 5 "general_operand" "idax")))]
+ "TARGET_AM33"
+ "or_lsr %2,%0,%5,%3"
+ [(set_attr "cc" "none")])
+
+ (define_insn "or_asl"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=&dax")
+ (ior:SI (match_operand:SI 1 "nonimmediate_operand" "0")
+ (match_operand:SI 2 "general_operand" "idax")))
+ (set (match_operand:SI 3 "nonimmediate_operand" "=&dax")
+ (ashift:SI (match_operand:SI 4 "nonimmediate_operand" "3")
+ (match_operand:SI 5 "general_operand" "idax")))]
+ "TARGET_AM33"
+ "or_asl %2,%0,%5,%3"
+ [(set_attr "cc" "none")])
+
+ (define_insn "xor_add"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=&dax")
+ (xor:SI (match_operand:SI 1 "nonimmediate_operand" "0")
+ (match_operand:SI 2 "general_operand" "idax")))
+ (set (match_operand:SI 3 "nonimmediate_operand" "=&dax")
+ (plus:SI (match_operand:SI 4 "nonimmediate_operand" "3")
+ (match_operand:SI 5 "general_operand" "idax")))]
+ "TARGET_AM33"
+ "xor_add %2,%0,%5,%3"
+ [(set_attr "cc" "none")])
+
+ (define_insn "xor_sub"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=&dax")
+ (xor:SI (match_operand:SI 1 "nonimmediate_operand" "0")
+ (match_operand:SI 2 "general_operand" "idax")))
+ (set (match_operand:SI 3 "nonimmediate_operand" "=&dax")
+ (minus:SI (match_operand:SI 4 "nonimmediate_operand" "3")
+ (match_operand:SI 5 "general_operand" "idax")))]
+ "TARGET_AM33"
+ "xor_sub %2,%0,%5,%3"
+ [(set_attr "cc" "none")])
+
+ (define_insn "xor_mov"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=&dax")
+ (xor:SI (match_operand:SI 1 "nonimmediate_operand" "0")
+ (match_operand:SI 2 "general_operand" "idax")))
+ (set (match_operand:SI 3 "nonimmediate_operand" "=&dax")
+ (match_operand:SI 5 "general_operand" "idax"))]
+ "TARGET_AM33"
+ "xor_mov %2,%0,%5,%3"
+ [(set_attr "cc" "none")])
+
+ (define_insn "xor_asr"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=&dax")
+ (xor:SI (match_operand:SI 1 "nonimmediate_operand" "0")
+ (match_operand:SI 2 "general_operand" "idax")))
+ (set (match_operand:SI 3 "nonimmediate_operand" "=&dax")
+ (ashiftrt:SI (match_operand:SI 4 "nonimmediate_operand" "3")
+ (match_operand:SI 5 "general_operand" "idax")))]
+ "TARGET_AM33"
+ "xor_asr %2,%0,%5,%3"
+ [(set_attr "cc" "none")])
+
+ (define_insn "xor_lsr"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=&dax")
+ (xor:SI (match_operand:SI 1 "nonimmediate_operand" "0")
+ (match_operand:SI 2 "general_operand" "idax")))
+ (set (match_operand:SI 3 "nonimmediate_operand" "=&dax")
+ (lshiftrt:SI (match_operand:SI 4 "nonimmediate_operand" "3")
+ (match_operand:SI 5 "general_operand" "idax")))]
+ "TARGET_AM33"
+ "xor_lsr %2,%0,%5,%3"
+ [(set_attr "cc" "none")])
+
+ (define_insn "xor_asl"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=&dax")
+ (xor:SI (match_operand:SI 1 "nonimmediate_operand" "0")
+ (match_operand:SI 2 "general_operand" "idax")))
+ (set (match_operand:SI 3 "nonimmediate_operand" "=&dax")
+ (ashift:SI (match_operand:SI 4 "nonimmediate_operand" "3")
+ (match_operand:SI 5 "general_operand" "idax")))]
+ "TARGET_AM33"
+ "xor_asl %2,%0,%5,%3"
+ [(set_attr "cc" "none")])
Index: t-mn10300
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/mn10300/t-mn10300,v
retrieving revision 1.6
diff -c -3 -p -r1.6 t-mn10300
*** t-mn10300 2000/08/07 11:20:25 1.6
--- t-mn10300 2000/08/31 19:02:58
*************** MULTILIB_DIRNAMES = am33
*** 24,26 ****
--- 24,28 ----
LIBGCC = stmp-multilib
INSTALL_LIBGCC = install-multilib
+
+ EXTRA_HEADERS = $(srcdir)/config/mn10300/dsp.h