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tm.texi REG_CLASS_CONTENTS documentation clarification
- To: gcc-patches at gcc dot gnu dot org
- Subject: tm.texi REG_CLASS_CONTENTS documentation clarification
- From: Michael Poole <poole at troilus dot org>
- Date: 02 Aug 2000 13:14:24 -0400
When I first tried to port gcc to a new target processor with more
than 32 registers, I found myself getting bitten mysteriously because
I had the masks in REG_CLASS_CONTENTS for the processor in the wrong
order. Might I suggest something like the below to clarify this case?
2000-08-02 Michael Poole <poole@troilus.org>
* tm.texi (Register Classes): Clarify order of sub-initializers
in REG_CLASS_CONTENTS.
Index: gcc/tm.texi
===================================================================
RCS file: /cvs/gcc/egcs/gcc/tm.texi,v
retrieving revision 1.134
diff -u -w -r1.134 tm.texi
--- tm.texi 2000/08/01 00:07:43 1.134
+++ tm.texi 2000/08/02 17:05:13
@@ -1828,6 +1828,9 @@
Then the integers are replaced by sub-initializers, braced groupings containing
several integers. Each sub-initializer must be suitable as an initializer
for the type @code{HARD_REG_SET} which is defined in @file{hard-reg-set.h}.
+In this situation, the first integer in each sub-initializer corresponds to
+registers 0 through 31, the second integer to registers 32 through 63, and
+so on.
@findex REGNO_REG_CLASS
@item REGNO_REG_CLASS (@var{regno})