This is the mail archive of the gcc-patches@gcc.gnu.org mailing list for the GCC project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]

SH patches checked in


These are two patches to the sh backend; both were approved by Richard
Henderson.
The first patch adds a new option, "-m4-nofpu".  The second patch
corrects a problem where expmed.c did not compute proper costs for
shifts, leading to lost optimizations.
I have not tested this as well as usual; I found that the current CVS
compiler generates an enormous amount of failures for the sh even
without this patch.  The compiler still builds with these patches, but
running the testsuite seemed entirely pointless.  I'll try to
investigate what's going wrong here.

Bernd

	From Joern Rennecke:
	* sh.h (CPP_SPEC, TARGET_SWITCHES): Add m4-nofpu.
	* sh.md (udivsi3, divsi3): Don't use libcalls that use the FPU
	unless TARGET_SH3E is set.
	* t-sh (MULTILIB_MATCHES): Add m2=m4-nofpu.

Index: t-sh
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/sh/t-sh,v
retrieving revision 1.5
diff -c -p -r1.5 t-sh
*** t-sh	1999/08/05 03:27:48	1.5
--- t-sh	2000/08/01 18:28:07
*************** fp-bit.c: $(srcdir)/config/fp-bit.c
*** 23,29 ****
  
  MULTILIB_OPTIONS= ml m2/m3e/m4-single-only/m4-single/m4
  MULTILIB_DIRNAMES= 
! MULTILIB_MATCHES = m2=m3
  
  LIBGCC = stmp-multilib
  INSTALL_LIBGCC = install-multilib
--- 23,29 ----
  
  MULTILIB_OPTIONS= ml m2/m3e/m4-single-only/m4-single/m4
  MULTILIB_DIRNAMES= 
! MULTILIB_MATCHES = m2=m3 m2=m4-nofpu
  
  LIBGCC = stmp-multilib
  INSTALL_LIBGCC = install-multilib
Index: sh.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/sh/sh.md,v
retrieving revision 1.36
diff -c -p -r1.36 sh.md
*** sh.md	2000/07/25 22:10:38	1.36
--- sh.md	2000/08/01 18:28:07
***************
*** 955,961 ****
  
    operands[3] = gen_reg_rtx(SImode);
    /* Emit the move of the address to a pseudo outside of the libcall.  */
!   if (TARGET_HARD_SH4)
      {
        emit_move_insn (operands[3],
  		      gen_rtx_SYMBOL_REF (SImode, \"__udivsi3_i4\"));
--- 955,961 ----
  
    operands[3] = gen_reg_rtx(SImode);
    /* Emit the move of the address to a pseudo outside of the libcall.  */
!   if (TARGET_HARD_SH4 && TARGET_SH3E)
      {
        emit_move_insn (operands[3],
  		      gen_rtx_SYMBOL_REF (SImode, \"__udivsi3_i4\"));
***************
*** 1041,1047 ****
  
    operands[3] = gen_reg_rtx(SImode);
    /* Emit the move of the address to a pseudo outside of the libcall.  */
!   if (TARGET_HARD_SH4)
      {
        emit_move_insn (operands[3],
  		      gen_rtx_SYMBOL_REF (SImode, \"__sdivsi3_i4\"));
--- 1041,1047 ----
  
    operands[3] = gen_reg_rtx(SImode);
    /* Emit the move of the address to a pseudo outside of the libcall.  */
!   if (TARGET_HARD_SH4 && TARGET_SH3E)
      {
        emit_move_insn (operands[3],
  		      gen_rtx_SYMBOL_REF (SImode, \"__sdivsi3_i4\"));
Index: sh.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/sh/sh.h,v
retrieving revision 1.64
diff -c -p -r1.64 sh.h
*** sh.h	2000/06/13 21:47:44	1.64
--- sh.h	2000/08/01 18:28:04
*************** extern int code_for_indirect_jump_scratc
*** 46,53 ****
  %{m3e:-D__SH3E__} \
  %{m4-single-only:-D__SH4_SINGLE_ONLY__} \
  %{m4-single:-D__SH4_SINGLE__} \
  %{m4:-D__SH4__} \
! %{!m1:%{!m2:%{!m3:%{!m3e:%{!m4:%{!m4-single:%{!m4-single-only:-D__sh1__}}}}}}} \
  %{mnomacsave:-D__NOMACSAVE__} \
  %{mhitachi:-D__HITACHI__}"
  
--- 46,54 ----
  %{m3e:-D__SH3E__} \
  %{m4-single-only:-D__SH4_SINGLE_ONLY__} \
  %{m4-single:-D__SH4_SINGLE__} \
+ %{m4-nofpu:-D__sh3__} \
  %{m4:-D__SH4__} \
! %{!m1:%{!m2:%{!m3:%{!m3e:%{!m4:%{!m4-single:%{!m4-single-only:%{!m4-nofpu:-D__sh1__}}}}}}}} \
  %{mnomacsave:-D__NOMACSAVE__} \
  %{mhitachi:-D__HITACHI__}"
  
*************** extern int target_flags;
*** 182,189 ****
    {"2",	        SH2_BIT},			\
    {"3",	        SH3_BIT|SH2_BIT},		\
    {"3e",	SH3E_BIT|SH3_BIT|SH2_BIT|FPU_SINGLE_BIT},	\
!   {"4-single-only",	SH3E_BIT|SH3_BIT|SH2_BIT|SH3E_BIT|HARD_SH4_BIT|FPU_SINGLE_BIT},	\
    {"4-single",	SH4_BIT|SH3E_BIT|SH3_BIT|SH2_BIT|HARD_SH4_BIT|FPU_SINGLE_BIT},\
    {"4",	        SH4_BIT|SH3E_BIT|SH3_BIT|SH2_BIT|HARD_SH4_BIT},	\
    {"b",		-LITTLE_ENDIAN_BIT},  		\
    {"bigtable", 	BIGTABLE_BIT},			\
--- 183,191 ----
    {"2",	        SH2_BIT},			\
    {"3",	        SH3_BIT|SH2_BIT},		\
    {"3e",	SH3E_BIT|SH3_BIT|SH2_BIT|FPU_SINGLE_BIT},	\
!   {"4-single-only",	SH3E_BIT|SH3_BIT|SH2_BIT|HARD_SH4_BIT|FPU_SINGLE_BIT},	\
    {"4-single",	SH4_BIT|SH3E_BIT|SH3_BIT|SH2_BIT|HARD_SH4_BIT|FPU_SINGLE_BIT},\
+   {"4-nofpu",	SH3_BIT|SH2_BIT|HARD_SH4_BIT},\
    {"4",	        SH4_BIT|SH3E_BIT|SH3_BIT|SH2_BIT|HARD_SH4_BIT},	\
    {"b",		-LITTLE_ENDIAN_BIT},  		\
    {"bigtable", 	BIGTABLE_BIT},			\


        * sh.md (ashlsi3_d, ashlsi3_k): Remove, replace with
	(ashlsi3_std): New pattern.
	(ashlsi3 expander): Use it for TARGET_SH3.
	* sh.c (gen_ashift): Use it instead of ashlsi3_k.

Index: sh.c
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/sh/sh.c,v
retrieving revision 1.54
diff -c -p -r1.54 sh.c
*** sh.c	2000/07/28 02:17:26	1.54
--- sh.c	2000/08/01 18:28:00
*************** gen_ashift (type, n, reg)
*** 1039,1045 ****
  	emit_insn (gen_lshrsi3_k (reg, reg, GEN_INT (n)));
        break;
      case ASHIFT:
!       emit_insn (gen_ashlsi3_k (reg, reg, GEN_INT (n)));
        break;
      }
  }
--- 1039,1045 ----
  	emit_insn (gen_lshrsi3_k (reg, reg, GEN_INT (n)));
        break;
      case ASHIFT:
!       emit_insn (gen_ashlsi3_std (reg, reg, GEN_INT (n)));
        break;
      }
  }
Index: sh.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/sh/sh.md,v
retrieving revision 1.36
diff -c -p -r1.36 sh.md
*** sh.md	2000/07/25 22:10:38	1.36
--- sh.md	2000/08/01 18:28:07
***************
*** 1525,1547 ****
  ;;
  ;; shift left
  
! (define_insn "ashlsi3_d"
!   [(set (match_operand:SI 0 "arith_reg_operand" "=r")
! 	(ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
! 		   (match_operand:SI 2 "arith_reg_operand" "r")))]
!   "TARGET_SH3"
!   "shld	%2,%0"
!   [(set_attr "type" "dyn_shift")])
! 
! (define_insn "ashlsi3_k"
!   [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
! 	(ashift:SI (match_operand:SI 1 "arith_reg_operand" "0,0")
! 		   (match_operand:SI 2 "const_int_operand" "M,K")))]
!   "CONST_OK_FOR_K (INTVAL (operands[2]))"
    "@
! 	add	%0,%0
! 	shll%O2	%0"
!   [(set_attr "type" "arith")])
  
  (define_insn "ashlhi3_k"
    [(set (match_operand:HI 0 "arith_reg_operand" "=r,r")
--- 1525,1556 ----
  ;;
  ;; shift left
  
! ;; This pattern is used by init_expmed for computing the costs of shift
! ;; insns.
! 
! (define_insn_and_split "ashlsi3_std"
!   [(set (match_operand:SI 0 "arith_reg_operand" "=r,r,r,r")
! 	(ashift:SI (match_operand:SI 1 "arith_reg_operand" "0,0,0,0")
! 		   (match_operand:SI 2 "nonmemory_operand" "r,M,K,?ri")))
!    (clobber (match_scratch:SI 3 "=X,X,X,&r"))]
!   "TARGET_SH3
!    || (GET_CODE (operands[2]) == CONST_INT
!        && CONST_OK_FOR_K (INTVAL (operands[2])))"
    "@
!    shld	%2,%0
!    add	%0,%0
!    shll%O2	%0
!    #"
!   "TARGET_SH3
!    && GET_CODE (operands[2]) == CONST_INT
!    && ! CONST_OK_FOR_K (INTVAL (operands[2]))"
!   [(set (match_dup 3) (match_dup 2))
!    (parallel
!     [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 3)))
!      (clobber (match_dup 4))])]
!   "operands[4] = gen_rtx_SCRATCH (SImode);"
!   [(set_attr "length" "*,*,*,4")
!    (set_attr "type" "dyn_shift,arith,arith,arith")])
  
  (define_insn "ashlhi3_k"
    [(set (match_operand:HI 0 "arith_reg_operand" "=r,r")
***************
*** 1594,1602 ****
    if (GET_CODE (operands[2]) == CONST_INT
        && sh_dynamicalize_shift_p (operands[2]))
      operands[2] = force_reg (SImode, operands[2]);
!   if (TARGET_SH3 && arith_reg_operand (operands[2], GET_MODE (operands[2])))
      {
!       emit_insn (gen_ashlsi3_d (operands[0], operands[1], operands[2]));
        DONE;
      }
    if (! immediate_operand (operands[2], GET_MODE (operands[2])))
--- 1603,1611 ----
    if (GET_CODE (operands[2]) == CONST_INT
        && sh_dynamicalize_shift_p (operands[2]))
      operands[2] = force_reg (SImode, operands[2]);
!   if (TARGET_SH3)
      {
!       emit_insn (gen_ashlsi3_std (operands[0], operands[1], operands[2]));
        DONE;
      }
    if (! immediate_operand (operands[2], GET_MODE (operands[2])))


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]