config/h8300/h8300.md: Add a new peephole optimization.

[Kazu Hirata <kazu at hxi dot com>]

Hi,

Attached is a patch to add a new peephole optimization to the h8300
target.

It combines an increment/decrement insn (adds #1, r0) and a test insn
(done by mov.w r0, r0) and emits inc.w r0. QI, HI, and SI modes are
covered.

The reason I used a peephole instead of changing the existing
(define_insn "addxx" ...) is that the target has used up all the
constraint letters for interger constants.  In order to implement
this, I needed a letter representing integer constants, -1 and -2, so
that I can use it for dec.[wl].

mov.[bwl] clears the overflow bit in cc0 regardless of operands.  The
inc/dec insn does set the overflow bit if an overflow occurs and
clears it if not.  We can ignore this difference because the overflow
bit is never used by gcc.  All other cc0 bits work identically.  Both
mov and inc/dec set the negative flag and the zero flag properly.

/* h8300-hms-gcc -Wall -O2 -fomit-frame-pointer */
void do_something ();

void
test (int n)
{
  if (--n)
    do_something ();
}


The above code gets compiled to:

/* Without the patch.  */
_test:
	subs	#1,er0 <- These two insns can be
	mov.w	r0,r0  <- combined to one dec.w.
	beq	.L3
	jsr	@_do_something
.L3:
	rts

/* With the patch.  */
_test:
	dec.w	#1,r0 <- Combined.
	beq	.L3
	jsr	@_do_something
.L3:
	rts

Thanks,

Kazu Hirata

===File ~/gnu/gcc/ChangeLog-incdec==========================
2000-07-13  Kazu Hirata  <kazu@hxi.com>

	* config/h8300/h8300.md: Add a new peephole optimization.

============================================================

===File ~/gnu/gcc/incdec.patch==============================
Index: h8300.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/h8300/h8300.md,v
retrieving revision 1.10
diff -u -r1.10 h8300.md
--- h8300.md	2000/05/18 16:58:03	1.10
+++ h8300.md	2000/07/14 05:25:23
@@ -2256,3 +2256,57 @@
   [(set_attr "length" "2")
    (set_attr "cc" "set_znv")])
 
+;; Notice a decrement (subs #1, er0) followed by a test (mov er0, er0).
+
+(define_peephole 
+  [(set (match_operand:QI 0 "register_operand" "")
+        (plus:QI (match_dup 0) (match_operand 1 "const_int_operand" "")))
+   (set (cc0)
+	(match_dup 0))]
+  "INTVAL (operands[1]) == 1
+   || INTVAL (operands[1]) == -1"
+  "*
+{
+  if (INTVAL (operands[1]) > 0)
+    return \"inc.b	%X0\";
+  else
+    return \"dec.b	%X0\";
+}"
+  [(set_attr "length" "2")
+   (set_attr "cc" "set_znv")])
+
+(define_peephole 
+  [(set (match_operand:HI 0 "register_operand" "")
+        (plus:HI (match_dup 0) (match_operand 1 "const_int_operand" "")))
+   (set (cc0)
+	(match_dup 0))]
+  "(TARGET_H8300H || TARGET_H8300S)
+   && (INTVAL (operands[1]) == 1 || INTVAL (operands[1]) == 2
+       || INTVAL (operands[1]) == -1 || INTVAL (operands[1]) == -2)"
+  "*
+{
+  if (INTVAL (operands[1]) > 0)
+    return \"inc.w	%1,%T0\";
+  else
+    return \"dec.w	%G1,%T0\";
+}"
+  [(set_attr "length" "2")
+   (set_attr "cc" "set_znv")])
+
+(define_peephole 
+  [(set (match_operand:SI 0 "register_operand" "")
+        (plus:SI (match_dup 0) (match_operand 1 "const_int_operand" "")))
+   (set (cc0)
+	(match_dup 0))]
+  "(TARGET_H8300H || TARGET_H8300S)
+   && (INTVAL (operands[1]) == 1 || INTVAL (operands[1]) == 2
+       || INTVAL (operands[1]) == -1 || INTVAL (operands[1]) == -2)"
+  "*
+{
+  if (INTVAL (operands[1]) > 0)
+    return \"inc.l	%1,%S0\";
+  else
+    return \"dec.l	%G1,%S0\";
+}"
+  [(set_attr "length" "2")
+   (set_attr "cc" "set_znv")])
============================================================