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Re: ARM: new peephole to turn {add,sub}+cmp into {add,sub}s
- To: Alexandre Oliva <aoliva at redhat dot com>
- Subject: Re: ARM: new peephole to turn {add,sub}+cmp into {add,sub}s
- From: Richard Earnshaw <rearnsha at arm dot com>
- Date: Fri, 07 Jul 2000 11:21:53 +0100
- Cc: gcc-patches at gcc dot gnu dot org
- Cc: rearnsha at arm dot com
- Organization: ARM Ltd.
- Reply-To: rearnsha at arm dot com
These are wrong. Consider the overflow case.
R.
> Even though combine attempts to merge add and sub with cmp, it won't
> do that if there are other insns between them. When the intervening
> insn is a store, it will typically be re-scheduled for execution after
> the cmp. Then, these new peepholes will match the sequence of add/sub
> and cmp and arrange for us to use adds/subs instead.
>
> Ok to install?
>
>
> Index: gcc/ChangeLog
> from Alexandre Oliva <aoliva@redhat.com>
>
> * config/arm/arm.md (adds, subs): Define peepholes.
>
> Index: gcc/config/arm/arm.md
> ===================================================================
> RCS file: /cvs/gcc/egcs/gcc/config/arm/arm.md,v
> retrieving revision 1.52
> diff -u -r1.52 arm.md
> --- gcc/config/arm/arm.md 2000/07/03 18:02:13 1.52
> +++ gcc/config/arm/arm.md 2000/07/06 20:03:58
> @@ -7793,6 +7793,28 @@
> "sub%?s\\t%0, %1, #0"
> [(set_attr "conds" "set")])
>
> +;; Combine may miss these because of intervening insns before sched.
> +
> +(define_peephole
> + [(set (match_operand:SI 0 "s_register_operand" "=r,r")
> + (plus:SI (match_operand:SI 1 "s_register_operand" "r,r")
> + (match_operand:SI 2 "arm_add_operand" "rI,L")))
> + (set (reg:CC 24)
> + (compare:CC (match_dup 0) (const_int 0)))]
> + ""
> + "add%?s\\t%0, %1, %2"
> +[(set_attr "conds" "set")])
> +
> +(define_peephole
> + [(set (match_operand:SI 0 "s_register_operand" "=r,r")
> + (minus:SI (match_operand:SI 1 "s_register_operand" "r,r")
> + (match_operand:SI 2 "arm_add_operand" "rI,L")))
> + (set (reg:CC 24)
> + (compare:CC (match_dup 0) (const_int 0)))]
> + ""
> + "sub%?s\\t%0, %1, %2"
> +[(set_attr "conds" "set")])
> +
> ; Peepholes to spot possible load- and store-multiples, if the ordering is
> ; reversed, check that the memory references aren't volatile.
>
>
>
> --
> Alexandre Oliva Enjoy Guarana', see http://www.ic.unicamp.br/~oliva/
> Red Hat GCC Developer aoliva@{cygnus.com, redhat.com}
> CS PhD student at IC-Unicamp oliva@{lsd.ic.unicamp.br, gnu.org}
> Free Software Evangelist *Please* write to mailing lists, not to me
>