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Re: Intel Pentium shift op patch
- To: Kultarr <kultarr at twobillsdrive dot com>
- Subject: Re: Intel Pentium shift op patch
- From: Jeffrey A Law <law at cygnus dot com>
- Date: Wed, 14 Jun 2000 15:15:29 -0600
- cc: gcc-patches at gcc dot gnu dot org
- Reply-To: law at cygnus dot com
In message <200006031921.PAA14697@aussie.speas.org>you write:
>
> Jeff,
>
> OK, I think this corrects all (most) of your objections. I have not
> filled out the copyright re-assignment form as of yet, but will do
> so assuming this change looks OK to you.
There's still a few issues that would need to be resolved. I'll go ahead
and point them out even though I'm testing a similar patch which addresses
all these problems.
> @@ -6309,6 +6309,21 @@
> (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
> (match_operand:QI 2 "nonmemory_operand" "I,c")))
> (clobber (reg:CC 17))]
> + "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
> + && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
> + && INTVAL(operands[2]) == 1"
> + "sar{l}\\t%0"
> + [(set_attr "type" "ishift")
> + (set (attr "length")
> + (if_then_else (match_operand:SI 0 "register_operand" "")
> + (const_string "2")
> + (const_string "*")))])
Operand 2 should only accept (const_int 1). This means you would need to
create a new predicate in i386.c. Which in turn means you need to add a
prototype for that new predicate in i386-protos.h. And anytime you add a
new predicate you need to update PREDICATE_CODES.
In general it's cleaner to use the right predicate than to try and
filter out invalid operands in the insn's condition.
Note that you do not need multiple alternatives since operand 2 should always
be (const_int 1). Thus you can (and should) simplify the constraints.
A nit, you wrote "INTVAL(operands[2) == 1" you always want a space between
the function/macro name and the open paren for its argument list. ie
"INTVAL (operands[2]) == 1" would be the correct format.
Most of the same comments also apply to the rotate instructions.
You missed half the places were we generate "sar" instructions, you didn't
fix any of the places wehre we generate "sal" or "shr" insns.
Here's the patch I'm currently testing (and will install if it passes
regression testing).
* i386.md: Create new [right,left] rotate and right shift
patterns to optimize shift by 1 bit for certain ia32 processors.
Update patterns which perform left shifts to optimize shift by
1 bit for certain ia32 processors.
* i386.c (const_int_1_operand): New predicate.
* i386.h (PREDICATE_CODES): Handle const_int_1_operand.
* i386-protos.h (const_int_1_operand): Prototype.
Index: i386-protos.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/i386/i386-protos.h,v
retrieving revision 1.20
diff -c -3 -p -r1.20 i386-protos.h
*** i386-protos.h 2000/06/01 14:41:31 1.20
--- i386-protos.h 2000/06/14 21:20:48
*************** extern int ix86_aligned_p PARAMS ((rtx))
*** 41,46 ****
--- 41,47 ----
extern int standard_80387_constant_p PARAMS ((rtx));
extern int symbolic_reference_mentioned_p PARAMS ((rtx));
+ extern int const_int_1_operand PARAMS ((rtx, enum machine_mode));
extern int symbolic_operand PARAMS ((rtx, enum machine_mode));
extern int pic_symbolic_operand PARAMS ((rtx, enum machine_mode));
extern int call_insn_operand PARAMS ((rtx, enum machine_mode));
Index: i386.c
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/i386/i386.c,v
retrieving revision 1.161
diff -c -3 -p -r1.161 i386.c
*** i386.c 2000/06/11 04:29:49 1.161
--- i386.c 2000/06/14 21:21:11
*************** function_arg (cum, mode, type, named)
*** 981,986 ****
--- 981,997 ----
return ret;
}
+
+ /* Return nonzero if OP is (const_int 1), else return zero. */
+
+ int
+ const_int_1_operand (op, mode)
+ rtx op;
+ enum machine_mode mode;
+ {
+ return (GET_CODE (op) == CONST_INT && INTVAL (op) == 1);
+ }
+
/* Returns 1 if OP is either a symbol reference or a sum of a symbol
reference and a constant. */
Index: i386.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/i386/i386.h,v
retrieving revision 1.117
diff -c -3 -p -r1.117 i386.h
*** i386.h 2000/06/11 04:29:49 1.117
--- i386.h 2000/06/14 21:21:36
*************** do { long l; \
*** 2496,2501 ****
--- 2496,2502 ----
/* Define the codes that are matched by predicates in i386.c. */
#define PREDICATE_CODES \
+ {"const_int_1_operand", {CONST_INT}}, \
{"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
{"aligned_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
LABEL_REF, SUBREG, REG, MEM}}, \
Index: i386.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/i386/i386.md,v
retrieving revision 1.157
diff -c -3 -p -r1.157 i386.md
*** i386.md 2000/06/01 14:41:31 1.157
--- i386.md 2000/06/14 21:22:12
***************
*** 5949,5954 ****
--- 5949,5958 ----
default:
if (REG_P (operands[2]))
return \"sal{l}\\t{%b2, %0|%0, %b2}\";
+ else if (GET_CODE (operands[2]) == CONST_INT
+ && INTVAL (operands[2]) == 1
+ && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
+ return \"sal{l}\\t%0\";
else
return \"sal{l}\\t{%2, %0|%0, %2}\";
}
***************
*** 6002,6007 ****
--- 6006,6015 ----
default:
if (REG_P (operands[2]))
return \"sal{l}\\t{%b2, %0|%0, %b2}\";
+ else if (GET_CODE (operands[2]) == CONST_INT
+ && INTVAL (operands[2]) == 1
+ && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
+ return \"sal{l}\\t%0\";
else
return \"sal{l}\\t{%2, %0|%0, %2}\";
}
***************
*** 6041,6046 ****
--- 6049,6058 ----
default:
if (REG_P (operands[2]))
return \"sal{w}\\t{%b2, %0|%0, %b2}\";
+ else if (GET_CODE (operands[2]) == CONST_INT
+ && INTVAL (operands[2]) == 1
+ && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
+ return \"sal{w}\\t%0\";
else
return \"sal{w}\\t{%2, %0|%0, %2}\";
}
***************
*** 6079,6084 ****
--- 6091,6100 ----
default:
if (REG_P (operands[2]))
return \"sal{w}\\t{%b2, %0|%0, %b2}\";
+ else if (GET_CODE (operands[2]) == CONST_INT
+ && INTVAL (operands[2]) == 1
+ && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
+ return \"sal{w}\\t%0\";
else
return \"sal{w}\\t{%2, %0|%0, %2}\";
}
***************
*** 6127,6132 ****
--- 6143,6157 ----
else
return \"sal{b}\\t{%b2, %0|%0, %b2}\";
}
+ else if (GET_CODE (operands[2]) == CONST_INT
+ && INTVAL (operands[2]) == 1
+ && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
+ {
+ if (NON_QI_REG_P (operands[1]))
+ return \"sal{l}\\t%0\";
+ else
+ return \"sal{b}\\t%0\";
+ }
else
{
if (NON_QI_REG_P (operands[1]))
***************
*** 6170,6175 ****
--- 6195,6204 ----
default:
if (REG_P (operands[2]))
return \"sal{b}\\t{%b2, %0|%0, %b2}\";
+ else if (GET_CODE (operands[2]) == CONST_INT
+ && INTVAL (operands[2]) == 1
+ && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
+ return \"sal{b}\\t%0\";
else
return \"sal{b}\\t{%2, %0|%0, %2}\";
}
***************
*** 6304,6309 ****
--- 6333,6352 ----
""
"ix86_expand_binary_operator (ASHIFTRT, SImode, operands); DONE;")
+ (define_insn "*ashrsi3_1_one_bit"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
+ (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
+ (match_operand:QI 2 "const_int_1_operand" "")))
+ (clobber (reg:CC 17))]
+ "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
+ && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
+ "sar{l}\\t%0"
+ [(set_attr "type" "ishift")
+ (set (attr "length")
+ (if_then_else (match_operand:SI 0 "register_operand" "")
+ (const_string "2")
+ (const_string "*")))])
+
(define_insn "*ashrsi3_1"
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
(ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
***************
*** 6318,6323 ****
--- 6361,6387 ----
;; This pattern can't accept a variable shift count, since shifts by
;; zero don't affect the flags. We assume that shifts by constant
;; zero are optimized away.
+ (define_insn "*ashrsi3_one_bit_cmpno"
+ [(set (reg 17)
+ (compare
+ (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
+ (match_operand:QI 2 "const_int_1_operand" ""))
+ (const_int 0)))
+ (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
+ (ashiftrt:SI (match_dup 1) (match_dup 2)))]
+ "ix86_match_ccmode (insn, CCNOmode)
+ && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
+ && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
+ "sar{l}\\t%0"
+ [(set_attr "type" "ishift")
+ (set (attr "length")
+ (if_then_else (match_operand:SI 0 "register_operand" "")
+ (const_string "2")
+ (const_string "*")))])
+
+ ;; This pattern can't accept a variable shift count, since shifts by
+ ;; zero don't affect the flags. We assume that shifts by constant
+ ;; zero are optimized away.
(define_insn "*ashrsi3_cmpno"
[(set (reg 17)
(compare
***************
*** 6340,6345 ****
--- 6404,6423 ----
"TARGET_HIMODE_MATH"
"ix86_expand_binary_operator (ASHIFTRT, HImode, operands); DONE;")
+ (define_insn "*ashrhi3_1_one_bit"
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
+ (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
+ (match_operand:QI 2 "const_int_1_operand" "")))
+ (clobber (reg:CC 17))]
+ "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)
+ && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
+ "sar{w}\\t%0"
+ [(set_attr "type" "ishift")
+ (set (attr "length")
+ (if_then_else (match_operand:SI 0 "register_operand" "")
+ (const_string "2")
+ (const_string "*")))])
+
(define_insn "*ashrhi3_1"
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
(ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
***************
*** 6354,6359 ****
--- 6432,6458 ----
;; This pattern can't accept a variable shift count, since shifts by
;; zero don't affect the flags. We assume that shifts by constant
;; zero are optimized away.
+ (define_insn "*ashrhi3_one_bit_cmpno"
+ [(set (reg 17)
+ (compare
+ (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
+ (match_operand:QI 2 "const_int_1_operand" ""))
+ (const_int 0)))
+ (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
+ (ashiftrt:HI (match_dup 1) (match_dup 2)))]
+ "ix86_match_ccmode (insn, CCNOmode)
+ && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
+ && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
+ "sar{w}\\t%0"
+ [(set_attr "type" "ishift")
+ (set (attr "length")
+ (if_then_else (match_operand:SI 0 "register_operand" "")
+ (const_string "2")
+ (const_string "*")))])
+
+ ;; This pattern can't accept a variable shift count, since shifts by
+ ;; zero don't affect the flags. We assume that shifts by constant
+ ;; zero are optimized away.
(define_insn "*ashrhi3_cmpno"
[(set (reg 17)
(compare
***************
*** 6376,6381 ****
--- 6475,6494 ----
"TARGET_QIMODE_MATH"
"ix86_expand_binary_operator (ASHIFTRT, QImode, operands); DONE;")
+ (define_insn "*ashrqi3_1_one_bit"
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
+ (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
+ (match_operand:QI 2 "const_int_1_operand" "")))
+ (clobber (reg:CC 17))]
+ "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)
+ && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
+ "sar{b}\\t%0"
+ [(set_attr "type" "ishift")
+ (set (attr "length")
+ (if_then_else (match_operand:SI 0 "register_operand" "")
+ (const_string "2")
+ (const_string "*")))])
+
(define_insn "*ashrqi3_1"
[(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
(ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
***************
*** 6390,6395 ****
--- 6503,6529 ----
;; This pattern can't accept a variable shift count, since shifts by
;; zero don't affect the flags. We assume that shifts by constant
;; zero are optimized away.
+ (define_insn "*ashrqi3_cmpno_one_bit"
+ [(set (reg 17)
+ (compare
+ (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
+ (match_operand:QI 2 "const_int_1_operand" "I"))
+ (const_int 0)))
+ (set (match_operand:QI 0 "nonimmediate_operand" "=rm")
+ (ashiftrt:QI (match_dup 1) (match_dup 2)))]
+ "ix86_match_ccmode (insn, CCNOmode)
+ && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
+ && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
+ "sar{b}\\t%0"
+ [(set_attr "type" "ishift")
+ (set (attr "length")
+ (if_then_else (match_operand:SI 0 "register_operand" "")
+ (const_string "2")
+ (const_string "*")))])
+
+ ;; This pattern can't accept a variable shift count, since shifts by
+ ;; zero don't affect the flags. We assume that shifts by constant
+ ;; zero are optimized away.
(define_insn "*ashrqi3_cmpno"
[(set (reg 17)
(compare
***************
*** 6469,6474 ****
--- 6603,6622 ----
""
"ix86_expand_binary_operator (LSHIFTRT, SImode, operands); DONE;")
+ (define_insn "*lshrsi3_1_one_bit"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
+ (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
+ (match_operand:QI 2 "const_int_1_operand" "")))
+ (clobber (reg:CC 17))]
+ "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
+ && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
+ "shr{l}\\t%0"
+ [(set_attr "type" "ishift")
+ (set (attr "length")
+ (if_then_else (match_operand:SI 0 "register_operand" "")
+ (const_string "2")
+ (const_string "*")))])
+
(define_insn "*lshrsi3_1"
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
(lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
***************
*** 6483,6488 ****
--- 6631,6657 ----
;; This pattern can't accept a variable shift count, since shifts by
;; zero don't affect the flags. We assume that shifts by constant
;; zero are optimized away.
+ (define_insn "*lshrsi3_cmpno_one_bit"
+ [(set (reg 17)
+ (compare
+ (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
+ (match_operand:QI 2 "const_int_1_operand" ""))
+ (const_int 0)))
+ (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
+ (lshiftrt:SI (match_dup 1) (match_dup 2)))]
+ "ix86_match_ccmode (insn, CCNOmode)
+ && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
+ && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
+ "shr{l}\\t%0"
+ [(set_attr "type" "ishift")
+ (set (attr "length")
+ (if_then_else (match_operand:SI 0 "register_operand" "")
+ (const_string "2")
+ (const_string "*")))])
+
+ ;; This pattern can't accept a variable shift count, since shifts by
+ ;; zero don't affect the flags. We assume that shifts by constant
+ ;; zero are optimized away.
(define_insn "*lshrsi3_cmpno"
[(set (reg 17)
(compare
***************
*** 6505,6510 ****
--- 6674,6693 ----
"TARGET_HIMODE_MATH"
"ix86_expand_binary_operator (LSHIFTRT, HImode, operands); DONE;")
+ (define_insn "*lshrhi3_1_one_bit"
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
+ (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
+ (match_operand:QI 2 "const_int_1_operand" "")))
+ (clobber (reg:CC 17))]
+ "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
+ && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
+ "shr{w}\\t%0"
+ [(set_attr "type" "ishift")
+ (set (attr "length")
+ (if_then_else (match_operand:SI 0 "register_operand" "")
+ (const_string "2")
+ (const_string "*")))])
+
(define_insn "*lshrhi3_1"
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
(lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
***************
*** 6519,6524 ****
--- 6702,6728 ----
;; This pattern can't accept a variable shift count, since shifts by
;; zero don't affect the flags. We assume that shifts by constant
;; zero are optimized away.
+ (define_insn "*lshrhi3_cmpno_one_bit"
+ [(set (reg 17)
+ (compare
+ (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
+ (match_operand:QI 2 "const_int_1_operand" ""))
+ (const_int 0)))
+ (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
+ (lshiftrt:HI (match_dup 1) (match_dup 2)))]
+ "ix86_match_ccmode (insn, CCNOmode)
+ && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
+ && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
+ "shr{w}\\t%0"
+ [(set_attr "type" "ishift")
+ (set (attr "length")
+ (if_then_else (match_operand:SI 0 "register_operand" "")
+ (const_string "2")
+ (const_string "*")))])
+
+ ;; This pattern can't accept a variable shift count, since shifts by
+ ;; zero don't affect the flags. We assume that shifts by constant
+ ;; zero are optimized away.
(define_insn "*lshrhi3_cmpno"
[(set (reg 17)
(compare
***************
*** 6541,6546 ****
--- 6745,6764 ----
"TARGET_QIMODE_MATH"
"ix86_expand_binary_operator (LSHIFTRT, QImode, operands); DONE;")
+ (define_insn "*lshrqi3_1_one_bit"
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
+ (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
+ (match_operand:QI 2 "const_int_1_operand" "")))
+ (clobber (reg:CC 17))]
+ "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)
+ && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
+ "shr{b}\\t%0"
+ [(set_attr "type" "ishift")
+ (set (attr "length")
+ (if_then_else (match_operand:SI 0 "register_operand" "")
+ (const_string "2")
+ (const_string "*")))])
+
(define_insn "*lshrqi3_1"
[(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
(lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
***************
*** 6555,6560 ****
--- 6773,6799 ----
;; This pattern can't accept a variable shift count, since shifts by
;; zero don't affect the flags. We assume that shifts by constant
;; zero are optimized away.
+ (define_insn "*lshrqi2_cmpno_one_bit"
+ [(set (reg 17)
+ (compare
+ (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
+ (match_operand:QI 2 "const_int_1_operand" ""))
+ (const_int 0)))
+ (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
+ (lshiftrt:QI (match_dup 1) (match_dup 2)))]
+ "ix86_match_ccmode (insn, CCNOmode)
+ && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
+ && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
+ "shr{b}\\t%0"
+ [(set_attr "type" "ishift")
+ (set (attr "length")
+ (if_then_else (match_operand:SI 0 "register_operand" "")
+ (const_string "2")
+ (const_string "*")))])
+
+ ;; This pattern can't accept a variable shift count, since shifts by
+ ;; zero don't affect the flags. We assume that shifts by constant
+ ;; zero are optimized away.
(define_insn "*lshrqi2_cmpno"
[(set (reg 17)
(compare
***************
*** 6578,6583 ****
--- 6817,6836 ----
""
"ix86_expand_binary_operator (ROTATE, SImode, operands); DONE;")
+ (define_insn "*rotlsi3_1_one_bit"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
+ (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0")
+ (match_operand:QI 2 "const_int_1_operand" "")))
+ (clobber (reg:CC 17))]
+ "ix86_binary_operator_ok (ROTATE, SImode, operands)
+ && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
+ "rol{l}\\t%0"
+ [(set_attr "type" "ishift")
+ (set (attr "length")
+ (if_then_else (match_operand:SI 0 "register_operand" "")
+ (const_string "2")
+ (const_string "*")))])
+
(define_insn "*rotlsi3_1"
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
(rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
***************
*** 6597,6602 ****
--- 6850,6869 ----
"TARGET_HIMODE_MATH"
"ix86_expand_binary_operator (ROTATE, HImode, operands); DONE;")
+ (define_insn "*rotlhi3_1_one_bit"
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
+ (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0")
+ (match_operand:QI 2 "const_int_1_operand" "")))
+ (clobber (reg:CC 17))]
+ "ix86_binary_operator_ok (ROTATE, HImode, operands)
+ && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
+ "rol{w}\\t%0"
+ [(set_attr "type" "ishift")
+ (set (attr "length")
+ (if_then_else (match_operand:SI 0 "register_operand" "")
+ (const_string "2")
+ (const_string "*")))])
+
(define_insn "*rotlhi3_1"
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
(rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
***************
*** 6616,6621 ****
--- 6883,6902 ----
"TARGET_QIMODE_MATH"
"ix86_expand_binary_operator (ROTATE, QImode, operands); DONE;")
+ (define_insn "*rotlqi3_1_one_bit"
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
+ (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0")
+ (match_operand:QI 2 "const_int_1_operand" "")))
+ (clobber (reg:CC 17))]
+ "ix86_binary_operator_ok (ROTATE, QImode, operands)
+ && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
+ "rol{b}\\t%0"
+ [(set_attr "type" "ishift")
+ (set (attr "length")
+ (if_then_else (match_operand:SI 0 "register_operand" "")
+ (const_string "2")
+ (const_string "*")))])
+
(define_insn "*rotlqi3_1"
[(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
(rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
***************
*** 6635,6640 ****
--- 6916,6935 ----
""
"ix86_expand_binary_operator (ROTATERT, SImode, operands); DONE;")
+ (define_insn "*rotrsi3_1_one_bit"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
+ (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0")
+ (match_operand:QI 2 "const_int_1_operand" "")))
+ (clobber (reg:CC 17))]
+ "ix86_binary_operator_ok (ROTATERT, SImode, operands)
+ && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
+ "ror{l}\\t%0"
+ [(set_attr "type" "ishift")
+ (set (attr "length")
+ (if_then_else (match_operand:SI 0 "register_operand" "")
+ (const_string "2")
+ (const_string "*")))])
+
(define_insn "*rotrsi3_1"
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
(rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
***************
*** 6654,6659 ****
--- 6949,6968 ----
"TARGET_HIMODE_MATH"
"ix86_expand_binary_operator (ROTATERT, HImode, operands); DONE;")
+ (define_insn "*rotrhi3_one_bit"
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
+ (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0")
+ (match_operand:QI 2 "const_int_1_operand" "")))
+ (clobber (reg:CC 17))]
+ "ix86_binary_operator_ok (ROTATERT, HImode, operands)
+ && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
+ "ror{w}\\t%0"
+ [(set_attr "type" "ishift")
+ (set (attr "length")
+ (if_then_else (match_operand:SI 0 "register_operand" "")
+ (const_string "2")
+ (const_string "*")))])
+
(define_insn "*rotrhi3"
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
(rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
***************
*** 6672,6677 ****
--- 6981,7000 ----
(clobber (reg:CC 17))]
"TARGET_QIMODE_MATH"
"ix86_expand_binary_operator (ROTATERT, QImode, operands); DONE;")
+
+ (define_insn "*rotrqi3_1_one_bit"
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
+ (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0")
+ (match_operand:QI 2 "const_int_1_operand" "")))
+ (clobber (reg:CC 17))]
+ "ix86_binary_operator_ok (ROTATERT, QImode, operands)
+ && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
+ "ror{b}\\t%0"
+ [(set_attr "type" "ishift")
+ (set (attr "length")
+ (if_then_else (match_operand:SI 0 "register_operand" "")
+ (const_string "2")
+ (const_string "*")))])
(define_insn "*rotrqi3_1"
[(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")