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alpha setcc movcc tweeks
- To: gcc-patches at gcc dot gnu dot org
- Subject: alpha setcc movcc tweeks
- From: Richard Henderson <rth at twiddle dot net>
- Date: Fri, 26 May 2000 00:06:35 -0700
Match more kinds of conditional moves and setcc output modes.
I saw at least a couple of cases of these in the gcc sources
that ifcvt can make use of.
r~
* config/alpha/alpha.c (alpha_comparison_operator): Don't be
so strict about DImode.
(alpha_swapped_comparison_operator): Likewise.
* config/alpha/alpha.md (*setne_internal): Name it. Allow
any integer output mode.
(*setcc_internal): Likewise.
(*setcc_swapped_internal): Likewise.
(*movdicc_internal, *movdicc_lbc, *movdicc_lbs): Name them.
(*mov[qhs]icc_internal): New.
(*mov[qhs]icc_lbc, *mov[qhs]icc_lbs): New.
Index: config/alpha/alpha.c
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/alpha/alpha.c,v
retrieving revision 1.130
diff -c -p -d -r1.130 alpha.c
*** alpha.c 2000/05/23 10:42:56 1.130
--- alpha.c 2000/05/26 06:36:27
*************** alpha_comparison_operator (op, mode)
*** 714,720 ****
return 0;
return (code == EQ || code == LE || code == LT
! || (mode == DImode && (code == LEU || code == LTU)));
}
/* Return 1 if OP is a valid Alpha swapped comparison operator. */
--- 714,720 ----
return 0;
return (code == EQ || code == LE || code == LT
! || code == LEU || code == LTU);
}
/* Return 1 if OP is a valid Alpha swapped comparison operator. */
*************** alpha_swapped_comparison_operator (op, m
*** 732,738 ****
code = swap_condition (code);
return (code == EQ || code == LE || code == LT
! || (mode == DImode && (code == LEU || code == LTU)));
}
/* Return 1 if OP is a signed comparison operation. */
--- 732,738 ----
code = swap_condition (code);
return (code == EQ || code == LE || code == LT
! || code == LEU || code == LTU);
}
/* Return 1 if OP is a signed comparison operation. */
Index: config/alpha/alpha.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/alpha/alpha.md,v
retrieving revision 1.118
diff -c -p -d -r1.118 alpha.md
*** alpha.md 2000/05/23 10:42:55 1.118
--- alpha.md 2000/05/26 06:36:28
***************
*** 2495,2530 ****
;; Next are all the integer comparisons, and conditional moves and branches
;; and some of the related define_expand's and define_split's.
! (define_insn ""
! [(set (match_operand:DI 0 "register_operand" "=r")
! (ne:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")
! (const_int 0)))]
! ""
"cmpult $31,%1,%0"
[(set_attr "type" "icmp")])
! (define_insn ""
! [(set (match_operand:DI 0 "register_operand" "=r")
! (match_operator:DI 1 "alpha_comparison_operator"
[(match_operand:DI 2 "reg_or_0_operand" "rJ")
(match_operand:DI 3 "reg_or_8bit_operand" "rI")]))]
! ""
"cmp%C1 %r2,%3,%0"
[(set_attr "type" "icmp")])
! (define_insn ""
! [(set (match_operand:DI 0 "register_operand" "=r")
! (match_operator:DI 1 "alpha_swapped_comparison_operator"
[(match_operand:DI 2 "reg_or_8bit_operand" "rI")
(match_operand:DI 3 "reg_or_0_operand" "rJ")]))]
! ""
"cmp%c1 %r3,%2,%0"
[(set_attr "type" "icmp")])
! ;; This pattern exists so conditional moves of SImode values are handled.
! ;; Comparisons are still done in DImode though.
! (define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
(if_then_else:SI
(match_operator 2 "signed_comparison_operator"
--- 2495,2568 ----
;; Next are all the integer comparisons, and conditional moves and branches
;; and some of the related define_expand's and define_split's.
! (define_insn "*setne_internal"
! [(set (match_operand 0 "register_operand" "=r")
! (ne (match_operand:DI 1 "reg_or_8bit_operand" "rI")
! (const_int 0)))]
! "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
! && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
! && GET_MODE (operands[0]) == GET_MODE (SET_SRC (PATTERN (insn)))"
"cmpult $31,%1,%0"
[(set_attr "type" "icmp")])
! (define_insn "*setcc_internal"
! [(set (match_operand 0 "register_operand" "=r")
! (match_operator 1 "alpha_comparison_operator"
[(match_operand:DI 2 "reg_or_0_operand" "rJ")
(match_operand:DI 3 "reg_or_8bit_operand" "rI")]))]
! "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
! && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
! && GET_MODE (operands[0]) == GET_MODE (operands[1])"
"cmp%C1 %r2,%3,%0"
[(set_attr "type" "icmp")])
! (define_insn "*setcc_swapped_internal"
! [(set (match_operand 0 "register_operand" "=r")
! (match_operator 1 "alpha_swapped_comparison_operator"
[(match_operand:DI 2 "reg_or_8bit_operand" "rI")
(match_operand:DI 3 "reg_or_0_operand" "rJ")]))]
! "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
! && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
! && GET_MODE (operands[0]) == GET_MODE (operands[1])"
"cmp%c1 %r3,%2,%0"
[(set_attr "type" "icmp")])
! ;; The mode folding trick can't be used with const_int operands, since
! ;; reload needs to know the proper mode.
! (define_insn "*movqicc_internal"
! [(set (match_operand:QI 0 "register_operand" "=r,r,r,r")
! (if_then_else:QI
! (match_operator 2 "signed_comparison_operator"
! [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
! (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
! (match_operand:QI 1 "reg_or_8bit_operand" "rI,0,rI,0")
! (match_operand:QI 5 "reg_or_8bit_operand" "0,rI,0,rI")))]
! "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
! "@
! cmov%C2 %r3,%1,%0
! cmov%D2 %r3,%5,%0
! cmov%c2 %r4,%1,%0
! cmov%d2 %r4,%5,%0"
! [(set_attr "type" "icmov")])
!
! (define_insn "*movhicc_internal"
! [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
! (if_then_else:HI
! (match_operator 2 "signed_comparison_operator"
! [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
! (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
! (match_operand:HI 1 "reg_or_8bit_operand" "rI,0,rI,0")
! (match_operand:HI 5 "reg_or_8bit_operand" "0,rI,0,rI")))]
! "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
! "@
! cmov%C2 %r3,%1,%0
! cmov%D2 %r3,%5,%0
! cmov%c2 %r4,%1,%0
! cmov%d2 %r4,%5,%0"
! [(set_attr "type" "icmov")])
!
! (define_insn "*movsicc_internal"
[(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
(if_then_else:SI
(match_operator 2 "signed_comparison_operator"
***************
*** 2532,2538 ****
(match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
(match_operand:SI 1 "reg_or_8bit_operand" "rI,0,rI,0")
(match_operand:SI 5 "reg_or_8bit_operand" "0,rI,0,rI")))]
! "operands[3] == const0_rtx || operands[4] == const0_rtx"
"@
cmov%C2 %r3,%1,%0
cmov%D2 %r3,%5,%0
--- 2570,2576 ----
(match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
(match_operand:SI 1 "reg_or_8bit_operand" "rI,0,rI,0")
(match_operand:SI 5 "reg_or_8bit_operand" "0,rI,0,rI")))]
! "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
"@
cmov%C2 %r3,%1,%0
cmov%D2 %r3,%5,%0
***************
*** 2540,2546 ****
cmov%d2 %r4,%5,%0"
[(set_attr "type" "icmov")])
! (define_insn ""
[(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
(if_then_else:DI
(match_operator 2 "signed_comparison_operator"
--- 2578,2584 ----
cmov%d2 %r4,%5,%0"
[(set_attr "type" "icmov")])
! (define_insn "*movdicc_internal"
[(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
(if_then_else:DI
(match_operator 2 "signed_comparison_operator"
***************
*** 2548,2554 ****
(match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
(match_operand:DI 1 "reg_or_8bit_operand" "rI,0,rI,0")
(match_operand:DI 5 "reg_or_8bit_operand" "0,rI,0,rI")))]
! "operands[3] == const0_rtx || operands[4] == const0_rtx"
"@
cmov%C2 %r3,%1,%0
cmov%D2 %r3,%5,%0
--- 2586,2592 ----
(match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
(match_operand:DI 1 "reg_or_8bit_operand" "rI,0,rI,0")
(match_operand:DI 5 "reg_or_8bit_operand" "0,rI,0,rI")))]
! "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
"@
cmov%C2 %r3,%1,%0
cmov%D2 %r3,%5,%0
***************
*** 2556,2562 ****
cmov%d2 %r4,%5,%0"
[(set_attr "type" "icmov")])
! (define_insn ""
[(set (match_operand:DI 0 "register_operand" "=r,r")
(if_then_else:DI
(eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
--- 2594,2645 ----
cmov%d2 %r4,%5,%0"
[(set_attr "type" "icmov")])
! (define_insn "*movqicc_lbc"
! [(set (match_operand:QI 0 "register_operand" "=r,r")
! (if_then_else:QI
! (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
! (const_int 1)
! (const_int 0))
! (const_int 0))
! (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
! (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
! ""
! "@
! cmovlbc %r2,%1,%0
! cmovlbs %r2,%3,%0"
! [(set_attr "type" "icmov")])
!
! (define_insn "*movhicc_lbc"
! [(set (match_operand:HI 0 "register_operand" "=r,r")
! (if_then_else:HI
! (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
! (const_int 1)
! (const_int 0))
! (const_int 0))
! (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
! (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
! ""
! "@
! cmovlbc %r2,%1,%0
! cmovlbs %r2,%3,%0"
! [(set_attr "type" "icmov")])
!
! (define_insn "*movsicc_lbc"
! [(set (match_operand:SI 0 "register_operand" "=r,r")
! (if_then_else:SI
! (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
! (const_int 1)
! (const_int 0))
! (const_int 0))
! (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
! (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
! ""
! "@
! cmovlbc %r2,%1,%0
! cmovlbs %r2,%3,%0"
! [(set_attr "type" "icmov")])
!
! (define_insn "*movdicc_lbc"
[(set (match_operand:DI 0 "register_operand" "=r,r")
(if_then_else:DI
(eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
***************
*** 2571,2577 ****
cmovlbs %r2,%3,%0"
[(set_attr "type" "icmov")])
! (define_insn ""
[(set (match_operand:DI 0 "register_operand" "=r,r")
(if_then_else:DI
(ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
--- 2654,2705 ----
cmovlbs %r2,%3,%0"
[(set_attr "type" "icmov")])
! (define_insn "*movqicc_lbs"
! [(set (match_operand:QI 0 "register_operand" "=r,r")
! (if_then_else:QI
! (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
! (const_int 1)
! (const_int 0))
! (const_int 0))
! (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
! (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
! ""
! "@
! cmovlbs %r2,%1,%0
! cmovlbc %r2,%3,%0"
! [(set_attr "type" "icmov")])
!
! (define_insn "*movhicc_lbs"
! [(set (match_operand:HI 0 "register_operand" "=r,r")
! (if_then_else:HI
! (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
! (const_int 1)
! (const_int 0))
! (const_int 0))
! (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
! (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
! ""
! "@
! cmovlbs %r2,%1,%0
! cmovlbc %r2,%3,%0"
! [(set_attr "type" "icmov")])
!
! (define_insn "*movsicc_lbs"
! [(set (match_operand:SI 0 "register_operand" "=r,r")
! (if_then_else:SI
! (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
! (const_int 1)
! (const_int 0))
! (const_int 0))
! (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
! (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
! ""
! "@
! cmovlbs %r2,%1,%0
! cmovlbc %r2,%3,%0"
! [(set_attr "type" "icmov")])
!
! (define_insn "*movdicc_lbs"
[(set (match_operand:DI 0 "register_operand" "=r,r")
(if_then_else:DI
(ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")