Re: proposal for new single-bit BImode for IA-64

[Alan Lehotsky <lehotsky at tiac dot net>]

At 20:32 -0700 5/1/00, Jim Wilson wrote:
....
>
>The problem isn't with gcse, it is with the use of CCmode in ia64.md.  CCmode
>is only supposed to be used with COMPARE, but ia64.md uses it with 
>EQ, NE, etc.
>The reason why CCmode was used is because IA-64 has a set of 64 single-bit
>predicate registers that hold the result of compares.  I need to be able to
>perform register allocation on these registers, so I need to use pseudo
>registers.  I can't use an integer mode like QImode or DImode, 
>because then the
>register allocator thinks it can put 8 or 64 bit values in the single-bit
>registers.  I can't use a partial integer mode like PDImode, because cse and
>combine refuse to perform some simplications because they don't know how many
>bits are in PDImode, and the result is that redundant compares don't get
>optimized away.  Now I see that I can't use CCmode either for the same reason.
>The only way I can see to make this work is to exactly describe what the
>hardware does (which is usually the right thing to do anyways), and 
>to do that,
>I need a new single-bit mode.

	Why can't you use QI and make the predicate registers part of
	a special class that has a unique constraint character.  If that
	constraint is only present in patterns that set or test the
	predicates, then you shouldn't find other values being assigned.

	I haven't looked at the IA64 port yet, but this would be a lot
	cleaner than adding BI mode. [Trust me on this, the SHARC
	port I mentioned had DM and PM modes added to support the
	Harvard architecture (two memory buses), and it's an endless
	mess.]

	The DSP port I maintain has 32 machine-dependent constraint
	characters to segregate register types.

	Al Lehotsky

	p.s.	Because psi.net maintains open relay mail servers, this
		message probably won't reach the mailing
		list, so if you "reply", try and quote enough material
		so that the rest of the  list knows what I was
		talking about....

	p.p.s.	I've been doing some work for Intel involving the IA64,
		and Mike Meissner has talked to me before about consulting
		with Cygnus.  Any chance you guys might be adding headcount
		soon on the Itanium?
-- 
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