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More PA64 infrastructure
- To: gcc-patches at gcc dot gnu dot org
- Subject: More PA64 infrastructure
- From: Jeffrey A Law <law at cygnus dot com>
- Date: Tue, 14 Mar 2000 08:38:59 -0700
- Reply-To: law at cygnus dot com
The PA32 and PA64 ports expose a different number of FP registers to GCC
to help with the issues surrounding SUBREGs of hard registers that are
smaller than word_size.
As a result, a number of macros which depend on register numbers need to
have different definitions for the PA32 and PA64 ports.
Rather than make pa.h a mass of spaghetti code with litterings of
(TARGET_64BIT ? X : Y) all over the place, it was easier to just put
the PA32 specific stuff in one file (pa32-regs.h) and the PA64 specific
stuff into another file (pa64-regs.h).
It means we can't have a single compiler that generates PA32 code or PA64
code based on a switch, but we couldn't before this change anyway due to
a number of factors that are unlikely to change.
This patch introduces the pa32-regs.h file and removes the appropriate macros
from pa.h and conditionalizes a few other bits of code that were not easily
moved into the paxx-regs.h file. The pa64-regs.h file will be contributed
with the rest of the PA64 port in the not too distant future.
* configure.in (hppa configurations): Add pa32-regs.h to the
list of tm files as appropriate.
* configure: Rebuilt.
* pa.c (compute_frame_size): Remove explicit knowledge about FP
register numbering.
(hppa_expand_prologue, hppa_expand_epilogue): Likewise.
(fmpyaddoperands, fmpysuboperands): Likewise.
* pa.h: Remove various definitions which depend on knowing
how registers are numbered.
* pa32-regs.h: New file with PA32 register numbering specific
definitions.
? config/pa/pa.c.SAVE
Index: configure.in
===================================================================
RCS file: /cvs/gcc/egcs/gcc/configure.in,v
retrieving revision 1.343
diff -c -3 -p -r1.343 configure.in
*** configure.in 2000/03/13 23:51:26 1.343
--- configure.in 2000/03/14 15:44:11
*************** changequote([,])dnl
*** 902,937 ****
;;
hppa1.1-*-pro*)
target_cpu_default="(MASK_JUMP_IN_DELAY | MASK_PORTABLE_RUNTIME | MASK_GAS
| MASK_NO_SPACE_REGS | MASK_SOFT_FLOAT)"
! tm_file="${tm_file} elfos.h pa/elf.h pa/pa-pro-end.h libgloss.h"
xm_file=pa/xm-papro.h
tmake_file=pa/t-pro
;;
hppa1.1-*-osf*)
target_cpu_default="MASK_PA_11"
! tm_file="${tm_file} pa/som.h pa/pa-osf.h"
use_collect2=yes
;;
hppa1.1-*-rtems*)
target_cpu_default="(MASK_JUMP_IN_DELAY | MASK_PORTABLE_RUNTIME | MASK_GAS
| MASK_NO_SPACE_REGS | MASK_SOFT_FLOAT)"
! tm_file="${tm_file} elfos.h pa/elf.h pa/pa-pro-end.h libgloss.h pa/rtems.h"
xm_file=pa/xm-papro.h
tmake_file=pa/t-pro
;;
hppa1.0-*-osf*)
! tm_file="${tm_file} pa/som.h pa/pa-osf.h"
use_collect2=yes
;;
hppa1.1-*-bsd*)
! tm_file="${tm_file} pa/som.h"
target_cpu_default="MASK_PA_11"
use_collect2=yes
;;
hppa1.0-*-bsd*)
! tm_file="${tm_file} pa/som.h"
use_collect2=yes
;;
hppa1.0-*-hpux7*)
! tm_file="pa/pa-oldas.h ${tm_file} pa/som.h pa/pa-hpux7.h"
xm_file=pa/xm-pahpux.h
xmake_file=pa/x-pa-hpux
if test x$gas = xyes
--- 902,937 ----
;;
hppa1.1-*-pro*)
target_cpu_default="(MASK_JUMP_IN_DELAY | MASK_PORTABLE_RUNTIME | MASK_GAS
| MASK_NO_SPACE_REGS | MASK_SOFT_FLOAT)"
! tm_file="${tm_file} pa/pa32-regs.h elfos.h pa/elf.h pa/pa-pro-end.h
libgloss.h"
xm_file=pa/xm-papro.h
tmake_file=pa/t-pro
;;
hppa1.1-*-osf*)
target_cpu_default="MASK_PA_11"
! tm_file="${tm_file} pa/pa32-regs.h pa/som.h pa/pa-osf.h"
use_collect2=yes
;;
hppa1.1-*-rtems*)
target_cpu_default="(MASK_JUMP_IN_DELAY | MASK_PORTABLE_RUNTIME | MASK_GAS
| MASK_NO_SPACE_REGS | MASK_SOFT_FLOAT)"
! tm_file="${tm_file} pa/pa32-regs.h elfos.h pa/elf.h pa/pa-pro-end.h
libgloss.h pa/rtems.h"
xm_file=pa/xm-papro.h
tmake_file=pa/t-pro
;;
hppa1.0-*-osf*)
! tm_file="${tm_file} pa/pa32-regs.h pa/som.h pa/pa-osf.h"
use_collect2=yes
;;
hppa1.1-*-bsd*)
! tm_file="${tm_file} pa/pa32-regs.h pa/som.h"
target_cpu_default="MASK_PA_11"
use_collect2=yes
;;
hppa1.0-*-bsd*)
! tm_file="${tm_file} pa/pa32-regs.h pa/som.h"
use_collect2=yes
;;
hppa1.0-*-hpux7*)
! tm_file="pa/pa-oldas.h ${tm_file} pa/pa32-regs.h pa/som.h pa/pa-hpux7.h"
xm_file=pa/xm-pahpux.h
xmake_file=pa/x-pa-hpux
if test x$gas = xyes
*************** changequote([,])dnl
*** 944,950 ****
changequote(,)dnl
hppa1.0-*-hpux8.0[0-2]*)
changequote([,])dnl
! tm_file="${tm_file} pa/som.h pa/pa-hpux.h"
xm_file=pa/xm-pahpux.h
xmake_file=pa/x-pa-hpux
if test x$gas = xyes
--- 944,950 ----
changequote(,)dnl
hppa1.0-*-hpux8.0[0-2]*)
changequote([,])dnl
! tm_file="${tm_file} pa/pa32-regs.h pa/som.h pa/pa-hpux.h"
xm_file=pa/xm-pahpux.h
xmake_file=pa/x-pa-hpux
if test x$gas = xyes
*************** changequote(,)dnl
*** 960,966 ****
hppa1.1-*-hpux8.0[0-2]*)
changequote([,])dnl
target_cpu_default="MASK_PA_11"
! tm_file="${tm_file} pa/som.h pa/pa-hpux.h"
xm_file=pa/xm-pahpux.h
xmake_file=pa/x-pa-hpux
if test x$gas = xyes
--- 960,966 ----
hppa1.1-*-hpux8.0[0-2]*)
changequote([,])dnl
target_cpu_default="MASK_PA_11"
! tm_file="${tm_file} pa/pa32-regs.h pa/som.h pa/pa-hpux.h"
xm_file=pa/xm-pahpux.h
xmake_file=pa/x-pa-hpux
if test x$gas = xyes
*************** changequote([,])dnl
*** 974,980 ****
;;
hppa1.1-*-hpux8*)
target_cpu_default="MASK_PA_11"
! tm_file="${tm_file} pa/som.h pa/pa-hpux.h"
xm_file=pa/xm-pahpux.h
xmake_file=pa/x-pa-hpux
if test x$gas = xyes
--- 974,980 ----
;;
hppa1.1-*-hpux8*)
target_cpu_default="MASK_PA_11"
! tm_file="${tm_file} pa/pa32-regs.h pa/som.h pa/pa-hpux.h"
xm_file=pa/xm-pahpux.h
xmake_file=pa/x-pa-hpux
if test x$gas = xyes
*************** changequote([,])dnl
*** 985,991 ****
use_collect2=yes
;;
hppa1.0-*-hpux8*)
! tm_file="${tm_file} pa/som.h pa/pa-hpux.h"
xm_file=pa/xm-pahpux.h
xmake_file=pa/x-pa-hpux
if test x$gas = xyes
--- 985,991 ----
use_collect2=yes
;;
hppa1.0-*-hpux8*)
! tm_file="${tm_file} pa/pa32-regs.h pa/som.h pa/pa-hpux.h"
xm_file=pa/xm-pahpux.h
xmake_file=pa/x-pa-hpux
if test x$gas = xyes
*************** changequote([,])dnl
*** 997,1003 ****
;;
hppa1.1-*-hpux10* | hppa2*-*-hpux10*)
target_cpu_default="MASK_PA_11"
! tm_file="${tm_file} pa/long_double.h pa/som.h pa/pa-hpux.h pa/pa-hpux10.h"
float_format=i128
xm_file=pa/xm-pahpux.h
xmake_file=pa/x-pa-hpux
--- 997,1003 ----
;;
hppa1.1-*-hpux10* | hppa2*-*-hpux10*)
target_cpu_default="MASK_PA_11"
! tm_file="${tm_file} pa/pa32-regs.h pa/long_double.h pa/som.h pa/pa-hpux.h
pa/pa-hpux10.h"
float_format=i128
xm_file=pa/xm-pahpux.h
xmake_file=pa/x-pa-hpux
*************** changequote([,])dnl
*** 1017,1023 ****
use_collect2=yes
;;
hppa1.0-*-hpux10*)
! tm_file="${tm_file} pa/long_double.h pa/som.h pa/pa-hpux.h pa/pa-hpux10.h"
float_format=i128
xm_file=pa/xm-pahpux.h
xmake_file=pa/x-pa-hpux
--- 1017,1023 ----
use_collect2=yes
;;
hppa1.0-*-hpux10*)
! tm_file="${tm_file} pa/pa32-regs.h pa/long_double.h pa/som.h pa/pa-hpux.h
pa/pa-hpux10.h"
float_format=i128
xm_file=pa/xm-pahpux.h
xmake_file=pa/x-pa-hpux
*************** changequote([,])dnl
*** 1038,1044 ****
;;
hppa1.1-*-hpux11* | hppa2*-*-hpux11*)
target_cpu_default="MASK_PA_11"
! tm_file="${tm_file} pa/long_double.h pa/som.h pa/pa-hpux.h pa/pa-hpux11.h"
float_format=i128
xm_file=pa/xm-pahpux.h
xmake_file=pa/x-pa-hpux
--- 1038,1044 ----
;;
hppa1.1-*-hpux11* | hppa2*-*-hpux11*)
target_cpu_default="MASK_PA_11"
! tm_file="${tm_file} pa/pa32-regs.h pa/long_double.h pa/som.h pa/pa-hpux.h
pa/pa-hpux11.h"
float_format=i128
xm_file=pa/xm-pahpux.h
xmake_file=pa/x-pa-hpux
*************** changequote([,])dnl
*** 1058,1064 ****
use_collect2=yes
;;
hppa1.0-*-hpux11*)
! tm_file="${tm_file} pa/long_double.h pa/som.h pa/pa-hpux.h pa/pa-hpux11.h"
float_format=i128
xm_file=pa/xm-pahpux.h
xmake_file=pa/x-pa-hpux
--- 1058,1064 ----
use_collect2=yes
;;
hppa1.0-*-hpux11*)
! tm_file="${tm_file} pa/pa32-regs.h pa/long_double.h pa/som.h pa/pa-hpux.h
pa/pa-hpux11.h"
float_format=i128
xm_file=pa/xm-pahpux.h
xmake_file=pa/x-pa-hpux
*************** changequote([,])dnl
*** 1078,1084 ****
;;
hppa1.1-*-hpux* | hppa2*-*-hpux*)
target_cpu_default="MASK_PA_11"
! tm_file="${tm_file} pa/som.h pa/pa-hpux.h pa/pa-hpux9.h"
xm_file=pa/xm-pahpux.h
xmake_file=pa/x-pa-hpux
if test x$gas = xyes
--- 1078,1084 ----
;;
hppa1.1-*-hpux* | hppa2*-*-hpux*)
target_cpu_default="MASK_PA_11"
! tm_file="${tm_file} pa/pa32-regs.h pa/som.h pa/pa-hpux.h pa/pa-hpux9.h"
xm_file=pa/xm-pahpux.h
xmake_file=pa/x-pa-hpux
if test x$gas = xyes
*************** changequote([,])dnl
*** 1089,1095 ****
use_collect2=yes
;;
hppa1.0-*-hpux*)
! tm_file="${tm_file} pa/som.h pa/pa-hpux.h pa/pa-hpux9.h"
xm_file=pa/xm-pahpux.h
xmake_file=pa/x-pa-hpux
if test x$gas = xyes
--- 1089,1095 ----
use_collect2=yes
;;
hppa1.0-*-hpux*)
! tm_file="${tm_file} pa/pa32-regs.h pa/som.h pa/pa-hpux.h pa/pa-hpux9.h"
xm_file=pa/xm-pahpux.h
xmake_file=pa/x-pa-hpux
if test x$gas = xyes
*************** changequote([,])dnl
*** 1101,1107 ****
;;
hppa1.1-*-hiux* | hppa2*-*-hiux*)
target_cpu_default="MASK_PA_11"
! tm_file="${tm_file} pa/som.h pa/pa-hpux.h pa/pa-hiux.h"
xm_file=pa/xm-pahpux.h
xmake_file=pa/x-pa-hpux
if test x$gas = xyes
--- 1101,1107 ----
;;
hppa1.1-*-hiux* | hppa2*-*-hiux*)
target_cpu_default="MASK_PA_11"
! tm_file="${tm_file} pa/pa32-regs.h pa/som.h pa/pa-hpux.h pa/pa-hiux.h"
xm_file=pa/xm-pahpux.h
xmake_file=pa/x-pa-hpux
if test x$gas = xyes
*************** changequote([,])dnl
*** 1112,1118 ****
use_collect2=yes
;;
hppa1.0-*-hiux*)
! tm_file="${tm_file} pa/som.h pa/pa-hpux.h pa/pa-hiux.h"
xm_file=pa/xm-pahpux.h
xmake_file=pa/x-pa-hpux
if test x$gas = xyes
--- 1112,1118 ----
use_collect2=yes
;;
hppa1.0-*-hiux*)
! tm_file="${tm_file} pa/pa32-regs.h pa/som.h pa/pa-hpux.h pa/pa-hiux.h"
xm_file=pa/xm-pahpux.h
xmake_file=pa/x-pa-hpux
if test x$gas = xyes
*************** changequote([,])dnl
*** 1123,1129 ****
use_collect2=yes
;;
hppa*-*-lites*)
! tm_file="${tm_file} elfos.h pa/elf.h"
target_cpu_default="MASK_PA_11"
use_collect2=yes
;;
--- 1123,1129 ----
use_collect2=yes
;;
hppa*-*-lites*)
! tm_file="${tm_file} pa/pa32-regs.h elfos.h pa/elf.h"
target_cpu_default="MASK_PA_11"
use_collect2=yes
;;
Index: config/pa/pa.c
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/pa/pa.c,v
retrieving revision 1.73
diff -c -3 -p -r1.73 pa.c
*** pa.c 2000/02/26 21:28:41 1.73
--- pa.c 2000/03/14 15:44:21
*************** compute_frame_size (size, fregs_live)
*** 2675,2681 ****
fsize = (fsize + 7) & ~7;
/* Account for space used by the callee floating point register saves. */
! for (i = 66; i >= 48; i -= 2)
if (regs_ever_live[i] || regs_ever_live[i + 1])
{
if (fregs_live)
--- 2675,2681 ----
fsize = (fsize + 7) & ~7;
/* Account for space used by the callee floating point register saves. */
! for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
if (regs_ever_live[i] || regs_ever_live[i + 1])
{
if (fregs_live)
*************** hppa_expand_prologue()
*** 2980,2986 ****
set_reg_plus_d (1, STACK_POINTER_REGNUM, offset);
/* Now actually save the FP registers. */
! for (i = 66; i >= 48; i -= 2)
{
if (regs_ever_live[i] || regs_ever_live[i + 1])
{
--- 2980,2986 ----
set_reg_plus_d (1, STACK_POINTER_REGNUM, offset);
/* Now actually save the FP registers. */
! for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
{
if (regs_ever_live[i] || regs_ever_live[i + 1])
{
*************** hppa_expand_epilogue ()
*** 3118,3124 ****
set_reg_plus_d (1, STACK_POINTER_REGNUM, offset);
/* Actually do the restores now. */
! for (i = 66; i >= 48; i -= 2)
{
if (regs_ever_live[i] || regs_ever_live[i + 1])
{
--- 3118,3124 ----
set_reg_plus_d (1, STACK_POINTER_REGNUM, offset);
/* Actually do the restores now. */
! for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
{
if (regs_ever_live[i] || regs_ever_live[i + 1])
{
*************** fmpyaddoperands (operands)
*** 5698,5709 ****
/* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
if (mode == SFmode
! && (REGNO (operands[0]) < 57
! || REGNO (operands[1]) < 57
! || REGNO (operands[2]) < 57
! || REGNO (operands[3]) < 57
! || REGNO (operands[4]) < 57
! || REGNO (operands[5]) < 57))
return 0;
/* Passed. Operands are suitable for fmpyadd. */
--- 5698,5709 ----
/* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
if (mode == SFmode
! && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
! || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
! || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
! || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
! || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
! || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
return 0;
/* Passed. Operands are suitable for fmpyadd. */
*************** fmpysuboperands (operands)
*** 5755,5766 ****
/* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
if (mode == SFmode
! && (REGNO (operands[0]) < 57
! || REGNO (operands[1]) < 57
! || REGNO (operands[2]) < 57
! || REGNO (operands[3]) < 57
! || REGNO (operands[4]) < 57
! || REGNO (operands[5]) < 57))
return 0;
/* Passed. Operands are suitable for fmpysub. */
--- 5755,5766 ----
/* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
if (mode == SFmode
! && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
! || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
! || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
! || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
! || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
! || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
return 0;
/* Passed. Operands are suitable for fmpysub. */
Index: config/pa/pa.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/pa/pa.h,v
retrieving revision 1.85
diff -c -3 -p -r1.85 pa.h
*** pa.h 2000/02/26 21:28:41 1.85
--- pa.h 2000/03/14 15:44:26
*************** extern int target_flags;
*** 227,244 ****
#define ASM_STABS_OP "\t.stabs"
#define ASM_STABN_OP "\t.stabn"
- /* How to renumber registers for dbx and gdb.
-
- Registers 0 - 31 remain unchanged.
-
- Registers 32 - 87 are mapped to 72 - 127
-
- Register 88 is mapped to 32. */
-
- #define DBX_REGISTER_NUMBER(REGNO) \
- ((REGNO) <= 31 ? (REGNO) : \
- ((REGNO) > 31 && (REGNO) <= 87 ? (REGNO) + 40 : 32))
-
/* GDB always assumes the current function's frame begins at the value
of the stack pointer upon entry to the current function. Accessing
local variables and parameters passed on the stack is done using the
--- 227,232 ----
*************** extern int target_flags;
*** 390,579 ****
/* Generate calls to memcpy, memcmp and memset. */
#define TARGET_MEM_FUNCTIONS
-
- /* Standard register usage. */
-
- /* Number of actual hardware registers.
- The hardware registers are assigned numbers for the compiler
- from 0 to just below FIRST_PSEUDO_REGISTER.
- All registers that the compiler knows about must be given numbers,
- even those that are not normally considered general registers.
-
- HP-PA 1.0 has 32 fullword registers and 16 floating point
- registers. The floating point registers hold either word or double
- word values.
-
- 16 additional registers are reserved.
-
- HP-PA 1.1 has 32 fullword registers and 32 floating point
- registers. However, the floating point registers behave
- differently: the left and right halves of registers are addressable
- as 32 bit registers. So, we will set things up like the 68k which
- has different fp units: define separate register sets for the 1.0
- and 1.1 fp units. */
-
- #define FIRST_PSEUDO_REGISTER 89 /* 32 general regs + 56 fp regs +
- + 1 shift reg */
-
- /* 1 for registers that have pervasive standard uses
- and are not available for the register allocator.
-
- On the HP-PA, these are:
- Reg 0 = 0 (hardware). However, 0 is used for condition code,
- so is not fixed.
- Reg 1 = ADDIL target/Temporary (hardware).
- Reg 2 = Return Pointer
- Reg 3 = Frame Pointer
- Reg 4 = Frame Pointer (>8k varying frame with HP compilers only)
- Reg 4-18 = Preserved Registers
- Reg 19 = Linkage Table Register in HPUX 8.0 shared library scheme.
- Reg 20-22 = Temporary Registers
- Reg 23-26 = Temporary/Parameter Registers
- Reg 27 = Global Data Pointer (hp)
- Reg 28 = Temporary/Return Value register
- Reg 29 = Temporary/Static Chain/Return Value register #2
- Reg 30 = stack pointer
- Reg 31 = Temporary/Millicode Return Pointer (hp)
-
- Freg 0-3 = Status Registers -- Not known to the compiler.
- Freg 4-7 = Arguments/Return Value
- Freg 8-11 = Temporary Registers
- Freg 12-15 = Preserved Registers
-
- Freg 16-31 = Reserved
-
- On the Snake, fp regs are
-
- Freg 0-3 = Status Registers -- Not known to the compiler.
- Freg 4L-7R = Arguments/Return Value
- Freg 8L-11R = Temporary Registers
- Freg 12L-21R = Preserved Registers
- Freg 22L-31R = Temporary Registers
-
- */
-
- #define FIXED_REGISTERS \
- {0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 1, 0, 0, 1, 0, \
- /* fp registers */ \
- 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, \
- 0}
-
- /* 1 for registers not available across function calls.
- These must include the FIXED_REGISTERS and also any
- registers that can be used without being saved.
- The latter must include the registers where values are returned
- and the register where structure-value addresses are passed.
- Aside from that, you can include as many other registers as you like. */
- #define CALL_USED_REGISTERS \
- {1, 1, 1, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 1, 1, 1, 1, 1, \
- 1, 1, 1, 1, 1, 1, 1, 1, \
- /* fp registers */ \
- 1, 1, 1, 1, 1, 1, 1, 1, \
- 1, 1, 1, 1, 1, 1, 1, 1, \
- 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 1, 1, 1, 1, \
- 1, 1, 1, 1, 1, 1, 1, 1, \
- 1, 1, 1, 1, 1, 1, 1, 1, \
- 1}
-
- #define CONDITIONAL_REGISTER_USAGE \
- { \
- if (!TARGET_PA_11) \
- { \
- for (i = 56; i < 88; i++) \
- fixed_regs[i] = call_used_regs[i] = 1; \
- for (i = 33; i < 88; i += 2) \
- fixed_regs[i] = call_used_regs[i] = 1; \
- } \
- if (TARGET_DISABLE_FPREGS || TARGET_SOFT_FLOAT)\
- { \
- for (i = 32; i < 88; i++) \
- fixed_regs[i] = call_used_regs[i] = 1; \
- } \
- if (flag_pic) \
- { \
- fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
- fixed_regs[PIC_OFFSET_TABLE_REGNUM_SAVED] = 1;\
- } \
- }
-
- /* Allocate the call used registers first. This should minimize
- the number of registers that need to be saved (as call used
- registers will generally not be allocated across a call).
-
- Experimentation has shown slightly better results by allocating
- FP registers first.
-
- FP registers are ordered so that all L registers are selected before
- R registers. This works around a false dependency interlock on the
- PA8000 when accessing the high and low parts of an FP register
- independently. */
-
- #define REG_ALLOC_ORDER \
- { \
- /* caller-saved fp regs. */ \
- 68, 70, 72, 74, 76, 78, 80, 82, \
- 84, 86, 40, 42, 44, 46, 32, 34, \
- 36, 38, \
- 69, 71, 73, 75, 77, 79, 81, 83, \
- 85, 87, 41, 43, 45, 47, 33, 35, \
- 37, 39, \
- /* caller-saved general regs. */ \
- 19, 20, 21, 22, 23, 24, 25, 26, \
- 27, 28, 29, 31, 2, \
- /* callee-saved fp regs. */ \
- 48, 50, 52, 54, 56, 58, 60, 62, \
- 64, 66, \
- 49, 51, 53, 55, 57, 59, 61, 63, \
- 65, 67, \
- /* callee-saved general regs. */ \
- 3, 4, 5, 6, 7, 8, 9, 10, \
- 11, 12, 13, 14, 15, 16, 17, 18, \
- /* special registers. */ \
- 1, 30, 0, 88}
-
- /* True if register is floating-point. */
- #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 87)
-
- /* Return number of consecutive hard regs needed starting at reg REGNO
- to hold something of mode MODE.
- This is ordinarily the length in words of a value of mode MODE
- but can be less for certain modes in special long registers.
-
- On the HP-PA, ordinary registers hold 32 bits worth;
- The floating point registers are 64 bits wide. Snake fp regs are 32
- bits wide */
- #define HARD_REGNO_NREGS(REGNO, MODE) \
- (FP_REGNO_P (REGNO) \
- ? (!TARGET_PA_11 ? 1 : (GET_MODE_SIZE (MODE) + 4 - 1) / 4) \
- : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
-
- /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
- On the HP-PA, the cpu registers can hold any mode. We
- force this to be an even register is it cannot hold the full mode. */
- #define HARD_REGNO_MODE_OK(REGNO, MODE) \
- ((REGNO) == 0 ? (MODE) == CCmode || (MODE) == CCFPmode \
- /* On 1.0 machines, don't allow wide non-fp modes in fp regs. */ \
- : !TARGET_PA_11 && FP_REGNO_P (REGNO) \
- ? GET_MODE_SIZE (MODE) <= 4 || GET_MODE_CLASS (MODE) == MODE_FLOAT \
- : FP_REGNO_P (REGNO) \
- ? GET_MODE_SIZE (MODE) <= 4 || ((REGNO) & 1) == 0 \
- /* Make wide modes be in aligned registers. */ \
- : GET_MODE_SIZE (MODE) <= UNITS_PER_WORD || ((REGNO) & 1) == 0)
-
/* Value is 1 if it is a good idea to tie two pseudo registers
when one has mode MODE1 and one has mode MODE2.
If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
--- 378,384 ----
*************** extern int target_flags;
*** 631,716 ****
is passed to a function. */
#define STRUCT_VALUE_REGNUM 28
- /* Define the classes of registers for register constraints in the
- machine description. Also define ranges of constants.
-
- One of the classes must always be named ALL_REGS and include all hard
regs.
- If there is more than one class, another class must be named NO_REGS
- and contain no registers.
-
- The name GENERAL_REGS must be the name of a class (or an alias for
- another name such as ALL_REGS). This is the class of registers
- that is allowed by "g" or "r" in a register constraint.
- Also, registers outside this class are allocated only when
- instructions express preferences for them.
-
- The classes must be numbered in nondecreasing order; that is,
- a larger-numbered class must never be contained completely
- in a smaller-numbered class.
-
- For any two classes, it is very desirable that there be another
- class that represents their union. */
-
- /* The HP-PA has four kinds of registers: general regs, 1.0 fp regs,
- 1.1 fp regs, and the high 1.1 fp regs, to which the operands of
- fmpyadd and fmpysub are restricted. */
-
- enum reg_class { NO_REGS, R1_REGS, GENERAL_REGS, FPUPPER_REGS, FP_REGS,
GENERAL_OR_FP_REGS,
- SHIFT_REGS, ALL_REGS, LIM_REG_CLASSES};
-
- #define N_REG_CLASSES (int) LIM_REG_CLASSES
-
- /* Give names of register classes as strings for dump file. */
-
- #define REG_CLASS_NAMES \
- {"NO_REGS", "R1_REGS", "GENERAL_REGS", "FPUPPER_REGS", "FP_REGS", \
- "GENERAL_OR_FP_REGS", "SHIFT_REGS", "ALL_REGS"}
-
- /* Define which registers fit in which classes.
- This is an initializer for a vector of HARD_REG_SET
- of length N_REG_CLASSES. Register 0, the "condition code" register,
- is in no class. */
-
- #define REG_CLASS_CONTENTS \
- {{0x00000000, 0x00000000, 0x00000000}, /* NO_REGS */ \
- {0x00000002, 0x00000000, 0x00000000}, /* R1_REGS */ \
- {0xfffffffe, 0x00000000, 0x00000000}, /* GENERAL_REGS */ \
- {0x00000000, 0xff000000, 0x00ffffff}, /* FPUPPER_REGS */ \
- {0x00000000, 0xffffffff, 0x00ffffff}, /* FP_REGS */ \
- {0xfffffffe, 0xffffffff, 0x00ffffff}, /* GENERAL_OR_FP_REGS */ \
- {0x00000000, 0x00000000, 0x01000000}, /* SHIFT_REGS */ \
- {0xfffffffe, 0xffffffff, 0x01ffffff}} /* ALL_REGS */
-
- /* The same information, inverted:
- Return the class number of the smallest class containing
- reg number REGNO. This could be a conditional expression
- or could index an array. */
-
- #define REGNO_REG_CLASS(REGNO) \
- ((REGNO) == 0 ? NO_REGS \
- : (REGNO) == 1 ? R1_REGS \
- : (REGNO) < 32 ? GENERAL_REGS \
- : (REGNO) < 56 ? FP_REGS \
- : (REGNO) < 88 ? FPUPPER_REGS \
- : SHIFT_REGS)
-
- /* The class value for index registers, and the one for base regs. */
- #define INDEX_REG_CLASS GENERAL_REGS
- #define BASE_REG_CLASS GENERAL_REGS
-
- #define FP_REG_CLASS_P(CLASS) \
- ((CLASS) == FP_REGS || (CLASS) == FPUPPER_REGS)
-
- /* Get reg_class from a letter such as appears in the machine description.
*/
- /* Keep 'x' for backward compatibility with user asm. */
- #define REG_CLASS_FROM_LETTER(C) \
- ((C) == 'f' ? FP_REGS : \
- (C) == 'y' ? FPUPPER_REGS : \
- (C) == 'x' ? FP_REGS : \
- (C) == 'q' ? SHIFT_REGS : \
- (C) == 'a' ? R1_REGS : \
- (C) == 'Z' ? ALL_REGS : NO_REGS)
-
/* The letters I, J, K, L and M in a register constraint string
can be used to stand for particular ranges of immediate operands.
This macro defines what the ranges are.
--- 436,441 ----
*************** enum reg_class { NO_REGS, R1_REGS, GENER
*** 747,752 ****
--- 472,487 ----
&& (VALUE) == CONST0_RTX (GET_MODE (VALUE))) \
: 0)
+ /* The class value for index registers, and the one for base regs. */
+ #define INDEX_REG_CLASS GENERAL_REGS
+ #define BASE_REG_CLASS GENERAL_REGS
+
+ #define FP_REG_CLASS_P(CLASS) \
+ ((CLASS) == FP_REGS || (CLASS) == FPUPPER_REGS)
+
+ /* True if register is floating-point. */
+ #define FP_REGNO_P(N) ((N) >= FP_REG_FIRST && (N) <= FP_REG_LAST)
+
/* Given an rtx X being reloaded into a reg required to be
in class CLASS, return the class of reg to actually use.
In general this is just CLASS; but on some machines
*************** enum reg_class { NO_REGS, R1_REGS, GENER
*** 773,785 ****
#define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
gen_rtx_MEM (MODE, gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-16)))
- /* Return the maximum number of consecutive registers
- needed to represent mode MODE in a register of class CLASS. */
- #define CLASS_MAX_NREGS(CLASS, MODE) \
- ((CLASS) == FP_REGS || (CLASS) == FPUPPER_REGS \
- ? (!TARGET_PA_11 ? 1 : (GET_MODE_SIZE (MODE) + 4 - 1) / 4) \
- : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
-
/* Stack layout; function entry, exit and calling. */
--- 508,513 ----
*************** enum reg_class { NO_REGS, R1_REGS, GENER
*** 855,861 ****
/* On the HP-PA the value is found in register(s) 28(-29), unless
the mode is SF or DF. Then the value is returned in fr4 (32, ) */
-
#define FUNCTION_VALUE(VALTYPE, FUNC) \
gen_rtx_REG (TYPE_MODE (VALTYPE), ((! TARGET_SOFT_FLOAT \
&& (TYPE_MODE (VALTYPE) == SFmode || \
--- 583,588 ----
*************** enum reg_class { NO_REGS, R1_REGS, GENER
*** 876,885 ****
#define FUNCTION_VALUE_REGNO_P(N) \
((N) == 28 || (! TARGET_SOFT_FLOAT && (N) == 32))
- /* 1 if N is a possible register number for function argument passing. */
-
- #define FUNCTION_ARG_REGNO_P(N) \
- (((N) >= 23 && (N) <= 26) || (! TARGET_SOFT_FLOAT && (N) >= 32 && (N) <=
39))
/* Define a data type for recording info about an argument list
during the scan of that argument list. This data type should
--- 603,608 ----
*************** while (0)
*** 1896,1928 ****
no longer contain unusual constructs. */
#define ASM_APP_OFF ""
-
- /* How to refer to registers in assembler output.
- This sequence is indexed by compiler's hard-register-number (see above).
*/
-
- #define REGISTER_NAMES \
- {"%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
\
- "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
\
- "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
\
- "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
\
- "%fr4", "%fr4R", "%fr5", "%fr5R", "%fr6", "%fr6R", "%fr7", "%fr7R",
\
- "%fr8", "%fr8R", "%fr9", "%fr9R", "%fr10", "%fr10R", "%fr11", "%fr11R",
\
- "%fr12", "%fr12R", "%fr13", "%fr13R", "%fr14", "%fr14R", "%fr15", "%fr15R",
\
- "%fr16", "%fr16R", "%fr17", "%fr17R", "%fr18", "%fr18R", "%fr19", "%fr19R",
\
- "%fr20", "%fr20R", "%fr21", "%fr21R", "%fr22", "%fr22R", "%fr23", "%fr23R",
\
- "%fr24", "%fr24R", "%fr25", "%fr25R", "%fr26", "%fr26R", "%fr27", "%fr27R",
\
- "%fr28", "%fr28R", "%fr29", "%fr29R", "%fr30", "%fr30R", "%fr31", "%fr31R",
\
- "SAR"}
-
- #define ADDITIONAL_REGISTER_NAMES \
- {{"%fr4L",32}, {"%fr5L",34}, {"%fr6L",36}, {"%fr7L",38}, \
- {"%fr8L",40}, {"%fr9L",42}, {"%fr10L",44}, {"%fr11L",46}, \
- {"%fr12L",48}, {"%fr13L",50}, {"%fr14L",52}, {"%fr15L",54}, \
- {"%fr16L",56}, {"%fr17L",58}, {"%fr18L",60}, {"%fr19L",62}, \
- {"%fr20L",64}, {"%fr21L",66}, {"%fr22L",68}, {"%fr23L",70}, \
- {"%fr24L",72}, {"%fr25L",74}, {"%fr26L",76}, {"%fr27L",78}, \
- {"%fr28L",80}, {"%fr29L",82}, {"%fr30L",84}, {"%fr31R",86}, \
- {"%cr11",88}}
/* This is how to output the definition of a user-level label named NAME,
such as the label on a static function or variable NAME. */
--- 1619,1624 ----
*** /dev/null Wed Mar 8 10:00:52 2000
--- config/pa/pa32-regs.h Wed Mar 1 16:36:45 2000
***************
*** 0 ****
--- 1,316 ----
+ /* Standard register usage. */
+
+ /* Number of actual hardware registers.
+ The hardware registers are assigned numbers for the compiler
+ from 0 to just below FIRST_PSEUDO_REGISTER.
+ All registers that the compiler knows about must be given numbers,
+ even those that are not normally considered general registers.
+
+ HP-PA 1.0 has 32 fullword registers and 16 floating point
+ registers. The floating point registers hold either word or double
+ word values.
+
+ 16 additional registers are reserved.
+
+ HP-PA 1.1 has 32 fullword registers and 32 floating point
+ registers. However, the floating point registers behave
+ differently: the left and right halves of registers are addressable
+ as 32 bit registers. So, we will set things up like the 68k which
+ has different fp units: define separate register sets for the 1.0
+ and 1.1 fp units. */
+
+ #define FIRST_PSEUDO_REGISTER 89 /* 32 general regs + 56 fp regs +
+ + 1 shift reg */
+
+ /* 1 for registers that have pervasive standard uses
+ and are not available for the register allocator.
+
+ On the HP-PA, these are:
+ Reg 0 = 0 (hardware). However, 0 is used for condition code,
+ so is not fixed.
+ Reg 1 = ADDIL target/Temporary (hardware).
+ Reg 2 = Return Pointer
+ Reg 3 = Frame Pointer
+ Reg 4 = Frame Pointer (>8k varying frame with HP compilers only)
+ Reg 4-18 = Preserved Registers
+ Reg 19 = Linkage Table Register in HPUX 8.0 shared library scheme.
+ Reg 20-22 = Temporary Registers
+ Reg 23-26 = Temporary/Parameter Registers
+ Reg 27 = Global Data Pointer (hp)
+ Reg 28 = Temporary/Return Value register
+ Reg 29 = Temporary/Static Chain/Return Value register #2
+ Reg 30 = stack pointer
+ Reg 31 = Temporary/Millicode Return Pointer (hp)
+
+ Freg 0-3 = Status Registers -- Not known to the compiler.
+ Freg 4-7 = Arguments/Return Value
+ Freg 8-11 = Temporary Registers
+ Freg 12-15 = Preserved Registers
+
+ Freg 16-31 = Reserved
+
+ On the Snake, fp regs are
+
+ Freg 0-3 = Status Registers -- Not known to the compiler.
+ Freg 4L-7R = Arguments/Return Value
+ Freg 8L-11R = Temporary Registers
+ Freg 12L-21R = Preserved Registers
+ Freg 22L-31R = Temporary Registers
+
+ */
+
+ #define FIXED_REGISTERS \
+ {0, 0, 0, 0, 0, 0, 0, 0, \
+ 0, 0, 0, 0, 0, 0, 0, 0, \
+ 0, 0, 0, 0, 0, 0, 0, 0, \
+ 0, 0, 0, 1, 0, 0, 1, 0, \
+ /* fp registers */ \
+ 0, 0, 0, 0, 0, 0, 0, 0, \
+ 0, 0, 0, 0, 0, 0, 0, 0, \
+ 0, 0, 0, 0, 0, 0, 0, 0, \
+ 0, 0, 0, 0, 0, 0, 0, 0, \
+ 0, 0, 0, 0, 0, 0, 0, 0, \
+ 0, 0, 0, 0, 0, 0, 0, 0, \
+ 0, 0, 0, 0, 0, 0, 0, 0, \
+ 0}
+
+ /* 1 for registers not available across function calls.
+ These must include the FIXED_REGISTERS and also any
+ registers that can be used without being saved.
+ The latter must include the registers where values are returned
+ and the register where structure-value addresses are passed.
+ Aside from that, you can include as many other registers as you like. */
+ #define CALL_USED_REGISTERS \
+ {1, 1, 1, 0, 0, 0, 0, 0, \
+ 0, 0, 0, 0, 0, 0, 0, 0, \
+ 0, 0, 0, 1, 1, 1, 1, 1, \
+ 1, 1, 1, 1, 1, 1, 1, 1, \
+ /* fp registers */ \
+ 1, 1, 1, 1, 1, 1, 1, 1, \
+ 1, 1, 1, 1, 1, 1, 1, 1, \
+ 0, 0, 0, 0, 0, 0, 0, 0, \
+ 0, 0, 0, 0, 0, 0, 0, 0, \
+ 0, 0, 0, 0, 1, 1, 1, 1, \
+ 1, 1, 1, 1, 1, 1, 1, 1, \
+ 1, 1, 1, 1, 1, 1, 1, 1, \
+ 1}
+
+ #define CONDITIONAL_REGISTER_USAGE \
+ { \
+ if (!TARGET_PA_11) \
+ { \
+ for (i = 56; i < 88; i++) \
+ fixed_regs[i] = call_used_regs[i] = 1; \
+ for (i = 33; i < 88; i += 2) \
+ fixed_regs[i] = call_used_regs[i] = 1; \
+ } \
+ if (TARGET_DISABLE_FPREGS || TARGET_SOFT_FLOAT)\
+ { \
+ for (i = 32; i < 88; i++) \
+ fixed_regs[i] = call_used_regs[i] = 1; \
+ } \
+ if (flag_pic) \
+ { \
+ fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
+ fixed_regs[PIC_OFFSET_TABLE_REGNUM_SAVED] = 1;\
+ } \
+ }
+
+ /* Allocate the call used registers first. This should minimize
+ the number of registers that need to be saved (as call used
+ registers will generally not be allocated across a call).
+
+ Experimentation has shown slightly better results by allocating
+ FP registers first.
+
+ FP registers are ordered so that all L registers are selected before
+ R registers. This works around a false dependency interlock on the
+ PA8000 when accessing the high and low parts of an FP register
+ independently. */
+
+ #define REG_ALLOC_ORDER \
+ { \
+ /* caller-saved fp regs. */ \
+ 68, 70, 72, 74, 76, 78, 80, 82, \
+ 84, 86, 40, 42, 44, 46, 32, 34, \
+ 36, 38, \
+ 69, 71, 73, 75, 77, 79, 81, 83, \
+ 85, 87, 41, 43, 45, 47, 33, 35, \
+ 37, 39, \
+ /* caller-saved general regs. */ \
+ 19, 20, 21, 22, 23, 24, 25, 26, \
+ 27, 28, 29, 31, 2, \
+ /* callee-saved fp regs. */ \
+ 48, 50, 52, 54, 56, 58, 60, 62, \
+ 64, 66, \
+ 49, 51, 53, 55, 57, 59, 61, 63, \
+ 65, 67, \
+ /* callee-saved general regs. */ \
+ 3, 4, 5, 6, 7, 8, 9, 10, \
+ 11, 12, 13, 14, 15, 16, 17, 18, \
+ /* special registers. */ \
+ 1, 30, 0, 88}
+
+
+ /* Return number of consecutive hard regs needed starting at reg REGNO
+ to hold something of mode MODE.
+ This is ordinarily the length in words of a value of mode MODE
+ but can be less for certain modes in special long registers.
+
+ On the HP-PA, ordinary registers hold 32 bits worth;
+ The floating point registers are 64 bits wide. Snake fp regs are 32
+ bits wide */
+ #define HARD_REGNO_NREGS(REGNO, MODE) \
+ (FP_REGNO_P (REGNO) \
+ ? (!TARGET_PA_11 ? 1 : (GET_MODE_SIZE (MODE) + 4 - 1) / 4) \
+ : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
+
+ /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
+ On the HP-PA, the cpu registers can hold any mode. We
+ force this to be an even register is it cannot hold the full mode. */
+ #define HARD_REGNO_MODE_OK(REGNO, MODE) \
+ ((REGNO) == 0 ? (MODE) == CCmode || (MODE) == CCFPmode \
+ /* On 1.0 machines, don't allow wide non-fp modes in fp regs. */ \
+ : !TARGET_PA_11 && FP_REGNO_P (REGNO) \
+ ? GET_MODE_SIZE (MODE) <= 4 || GET_MODE_CLASS (MODE) == MODE_FLOAT \
+ : FP_REGNO_P (REGNO) \
+ ? GET_MODE_SIZE (MODE) <= 4 || ((REGNO) & 1) == 0 \
+ /* Make wide modes be in aligned registers. */ \
+ : (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD \
+ || GET_MODE_SIZE (MODE) <= 2 * UNITS_PER_WORD && ((REGNO) & 1) == 0))
+
+ /* How to renumber registers for dbx and gdb.
+
+ Registers 0 - 31 remain unchanged.
+
+ Registers 32 - 87 are mapped to 72 - 127
+
+ Register 88 is mapped to 32. */
+
+ #define DBX_REGISTER_NUMBER(REGNO) \
+ ((REGNO) <= 31 ? (REGNO) : \
+ ((REGNO) > 31 && (REGNO) <= 87 ? (REGNO) + 40 : 32))
+
+ /* Define the classes of registers for register constraints in the
+ machine description. Also define ranges of constants.
+
+ One of the classes must always be named ALL_REGS and include all hard
regs.
+ If there is more than one class, another class must be named NO_REGS
+ and contain no registers.
+
+ The name GENERAL_REGS must be the name of a class (or an alias for
+ another name such as ALL_REGS). This is the class of registers
+ that is allowed by "g" or "r" in a register constraint.
+ Also, registers outside this class are allocated only when
+ instructions express preferences for them.
+
+ The classes must be numbered in nondecreasing order; that is,
+ a larger-numbered class must never be contained completely
+ in a smaller-numbered class.
+
+ For any two classes, it is very desirable that there be another
+ class that represents their union. */
+
+ /* The HP-PA has four kinds of registers: general regs, 1.0 fp regs,
+ 1.1 fp regs, and the high 1.1 fp regs, to which the operands of
+ fmpyadd and fmpysub are restricted. */
+
+ enum reg_class { NO_REGS, R1_REGS, GENERAL_REGS, FPUPPER_REGS, FP_REGS,
+ GENERAL_OR_FP_REGS, SHIFT_REGS, ALL_REGS, LIM_REG_CLASSES};
+
+ #define N_REG_CLASSES (int) LIM_REG_CLASSES
+
+ /* Give names of register classes as strings for dump file. */
+
+ #define REG_CLASS_NAMES \
+ {"NO_REGS", "R1_REGS", "GENERAL_REGS", "FPUPPER_REGS", "FP_REGS", \
+ "GENERAL_OR_FP_REGS", "SHIFT_REGS", "ALL_REGS"}
+
+ /* Define which registers fit in which classes.
+ This is an initializer for a vector of HARD_REG_SET
+ of length N_REG_CLASSES. Register 0, the "condition code" register,
+ is in no class. */
+
+ #define REG_CLASS_CONTENTS \
+ {{0x00000000, 0x00000000, 0x00000000}, /* NO_REGS */ \
+ {0x00000002, 0x00000000, 0x00000000}, /* R1_REGS */ \
+ {0xfffffffe, 0x00000000, 0x00000000}, /* GENERAL_REGS */ \
+ {0x00000000, 0xff000000, 0x00ffffff}, /* FPUPPER_REGS */ \
+ {0x00000000, 0xffffffff, 0x00ffffff}, /* FP_REGS */ \
+ {0xfffffffe, 0xffffffff, 0x00ffffff}, /* GENERAL_OR_FP_REGS */ \
+ {0x00000000, 0x00000000, 0x01000000}, /* SHIFT_REGS */ \
+ {0xfffffffe, 0xffffffff, 0x01ffffff}} /* ALL_REGS */
+
+ /* This may not actually be necessary anymore. But until I can prove
+ otherwise it will stay. */
+ #define CLASS_CANNOT_CHANGE_SIZE NO_REGS
+
+ /* The same information, inverted:
+ Return the class number of the smallest class containing
+ reg number REGNO. This could be a conditional expression
+ or could index an array. */
+
+ #define REGNO_REG_CLASS(REGNO) \
+ ((REGNO) == 0 ? NO_REGS \
+ : (REGNO) == 1 ? R1_REGS \
+ : (REGNO) < 32 ? GENERAL_REGS \
+ : (REGNO) < 56 ? FP_REGS \
+ : (REGNO) < 88 ? FPUPPER_REGS \
+ : (REGNO) < 88 ? FPUPPER_REGS \
+ : SHIFT_REGS)
+
+ /* Get reg_class from a letter such as appears in the machine description.
*/
+ /* Keep 'x' for backward compatibility with user asm. */
+ #define REG_CLASS_FROM_LETTER(C) \
+ ((C) == 'f' ? FP_REGS : \
+ (C) == 'y' ? FPUPPER_REGS : \
+ (C) == 'y' ? FPUPPER_REGS : \
+ (C) == 'x' ? FP_REGS : \
+ (C) == 'q' ? SHIFT_REGS : \
+ (C) == 'a' ? R1_REGS : \
+ (C) == 'Z' ? ALL_REGS : NO_REGS)
+
+ /* Return the maximum number of consecutive registers
+ needed to represent mode MODE in a register of class CLASS. */
+ #define CLASS_MAX_NREGS(CLASS, MODE) \
+ ((CLASS) == FP_REGS || (CLASS) == FPUPPER_REGS \
+ ? (!TARGET_PA_11 ? 1 : (GET_MODE_SIZE (MODE) + 4 - 1) / 4) \
+ : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
+
+ /* 1 if N is a possible register number for function argument passing. */
+
+ #define FUNCTION_ARG_REGNO_P(N) \
+ (((N) >= 23 && (N) <= 26) || (! TARGET_SOFT_FLOAT && (N) >= 32 && (N) <=
39))
+
+ /* How to refer to registers in assembler output.
+ This sequence is indexed by compiler's hard-register-number (see above).
*/
+
+ #define REGISTER_NAMES \
+ {"%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
\
+ "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
\
+ "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
\
+ "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
\
+ "%fr4", "%fr4R", "%fr5", "%fr5R", "%fr6", "%fr6R", "%fr7", "%fr7R",
\
+ "%fr8", "%fr8R", "%fr9", "%fr9R", "%fr10", "%fr10R", "%fr11", "%fr11R",
\
+ "%fr12", "%fr12R", "%fr13", "%fr13R", "%fr14", "%fr14R", "%fr15", "%fr15R",
\
+ "%fr16", "%fr16R", "%fr17", "%fr17R", "%fr18", "%fr18R", "%fr19", "%fr19R",
\
+ "%fr20", "%fr20R", "%fr21", "%fr21R", "%fr22", "%fr22R", "%fr23", "%fr23R",
\
+ "%fr24", "%fr24R", "%fr25", "%fr25R", "%fr26", "%fr26R", "%fr27", "%fr27R",
\
+ "%fr28", "%fr28R", "%fr29", "%fr29R", "%fr30", "%fr30R", "%fr31", "%fr31R",
\
+ "SAR"}
+
+ #define ADDITIONAL_REGISTER_NAMES \
+ {{"%fr4L",32}, {"%fr5L",34}, {"%fr6L",36}, {"%fr7L",38}, \
+ {"%fr8L",40}, {"%fr9L",42}, {"%fr10L",44}, {"%fr11L",46}, \
+ {"%fr12L",48}, {"%fr13L",50}, {"%fr14L",52}, {"%fr15L",54}, \
+ {"%fr16L",56}, {"%fr17L",58}, {"%fr18L",60}, {"%fr19L",62}, \
+ {"%fr20L",64}, {"%fr21L",66}, {"%fr22L",68}, {"%fr23L",70}, \
+ {"%fr24L",72}, {"%fr25L",74}, {"%fr26L",76}, {"%fr27L",78}, \
+ {"%fr28L",80}, {"%fr29L",82}, {"%fr30L",84}, {"%fr31R",86}, \
+ {"%cr11",88}}
+
+ #define FP_SAVED_REG_LAST 66
+ #define FP_SAVED_REG_FIRST 48
+ #define FP_REG_STEP 2
+ #define FP_REG_FIRST 32
+ #define FP_REG_LAST 87