Re: Bootstrap ICE on alpha-osf4 building stage1 libgcc.a

[Richard Henderson <rth at cygnus dot com>]

On Mon, Jan 24, 2000 at 11:58:13AM -0500, Kaveh R. Ghazi wrote:
>  > ../../egcs-CVS20000124/gcc/libgcc2.c: In function `__fixunsdfdi':
>  > ../../egcs-CVS20000124/gcc/libgcc2.c:974: Internal compiler error in
>  > 	`?', at config/alpha/alpha.c:1882

Fixed thus.  Sort of irritating that optabs always prefers to widen
to TFmode instead of implementing with two DFmode conversions.

This should work though, and it'd be nice to verify that it does
before I go in and force the old behaviour.


r~


        * alpha.c (alpha_emit_xfloating_cvt): Thinko in operand manipulation.
        * alpha.md (movtf): New expander, insn, and splitter.

Index: config/alpha/alpha.c
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/alpha/alpha.c,v
retrieving revision 1.108
diff -c -p -d -r1.108 alpha.c
*** alpha.c	2000/01/24 04:02:40	1.108
--- alpha.c	2000/01/24 19:48:58
*************** alpha_emit_xfloating_cvt (code, operands
*** 1971,1981 ****
      {
      case FIX:
        mode = alpha_compute_xfloating_mode_arg (code, ALPHA_FPRM_CHOP);
!       operands[noperands++] = GEN_INT (mode);
        break;
      case FLOAT_TRUNCATE:
        mode = alpha_compute_xfloating_mode_arg (code, alpha_fprm);
!       operands[noperands++] = GEN_INT (mode);
        break;
      default:
        break;
--- 1971,1983 ----
      {
      case FIX:
        mode = alpha_compute_xfloating_mode_arg (code, ALPHA_FPRM_CHOP);
!       operands[2] = GEN_INT (mode);
!       noperands = 2;
        break;
      case FLOAT_TRUNCATE:
        mode = alpha_compute_xfloating_mode_arg (code, alpha_fprm);
!       operands[2] = GEN_INT (mode);
!       noperands = 2;
        break;
      default:
        break;
Index: config/alpha/alpha.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/alpha/alpha.md,v
retrieving revision 1.102
diff -c -p -d -r1.102 alpha.md
*** alpha.md	2000/01/24 04:02:40	1.102
--- alpha.md	2000/01/24 19:48:59
***************
*** 4076,4081 ****
--- 4076,4132 ----
     ftoit %1,%0"
    [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
  
+ ;; Subregs suck for register allocation.  Pretend we can move TFmode
+ ;; data between general registers until after reload.
+ (define_insn ""
+   [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o")
+ 	(match_operand:TF 1 "input_operand" "ro,r"))]
+   "register_operand (operands[0], TFmode)
+    || reg_or_fp0_operand (operands[1], TFmode)"
+   "#")
+ 
+ (define_split
+   [(set (match_operand:TF 0 "nonimmediate_operand" "")
+ 	(match_operand:TF 1 "input_operand" ""))]
+   "reload_completed"
+   [(set (match_dup 0) (match_dup 2))
+    (set (match_dup 1) (match_dup 3))]
+   "
+ {
+   if (GET_CODE (operands[1]) == REG)
+     {
+       operands[3] = gen_rtx_REG (DImode, REGNO (operands[1]) + 1);
+       operands[2] = gen_rtx_REG (DImode, REGNO (operands[1]));
+     }
+   else if (GET_CODE (operands[1]) == MEM)
+     {
+       operands[3] = change_address (operands[1], DImode,
+ 				    plus_constant (XEXP (operands[1], 0), 8));
+       operands[2] = change_address (operands[1], DImode, NULL_RTX);
+     }
+ 
+   if (GET_CODE (operands[0]) == REG)
+     {
+       operands[1] = gen_rtx_REG (DImode, REGNO (operands[0]) + 1);
+       operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
+     }
+   else if (GET_CODE (operands[0]) == MEM)
+     {
+       operands[1] = change_address (operands[0], DImode,
+ 				    plus_constant (XEXP (operands[0], 0), 8));
+       operands[0] = change_address (operands[0], DImode, NULL_RTX);
+     }
+ 
+   if (rtx_equal_p (operands[0], operands[3]))
+     {
+       rtx tmp;
+       tmp = operands[0], operands[0] = operands[1], operands[1] = tmp;
+       tmp = operands[2], operands[2] = operands[3], operands[3] = tmp;
+     }
+ }")
+ 
+ 
+ 
  (define_expand "movsf"
    [(set (match_operand:SF 0 "nonimmediate_operand" "")
  	(match_operand:SF 1 "general_operand" ""))]
***************
*** 4096,4101 ****
--- 4147,4163 ----
    if (GET_CODE (operands[0]) == MEM
        && ! reg_or_fp0_operand (operands[1], DFmode))
      operands[1] = force_reg (DFmode, operands[1]);
+ }")
+ 
+ (define_expand "movtf"
+   [(set (match_operand:TF 0 "nonimmediate_operand" "")
+ 	(match_operand:TF 1 "general_operand" ""))]
+   ""
+   "
+ {
+   if (GET_CODE (operands[0]) == MEM
+       && ! reg_or_fp0_operand (operands[1], TFmode))
+     operands[1] = force_reg (TFmode, operands[1]);
  }")
  
  (define_insn ""