Re: [PATCH] Sparc floating point optimizations

["David S. Miller" <davem at redhat dot com>]

   Date: Wed, 8 Dec 1999 01:00:38 -0800
   From: Richard Henderson <rth@cygnus.com>

   On Wed, Dec 08, 1999 at 12:58:04AM -0800, David S. Miller wrote:
   > Oh I see, make toplevel insns which list the full set of alternatives
   > available for a given combination of target flags which matter, these
   > get matched early on and then later alternative switching takes place
   > within this single pattern during reload.

   Exactly.

I'm having some troubles getting this to work the way we need
it too.

The problem is how the expression's rtl is created by the fontend
to backend rtl generation layer.  We get something like:

    extern float x;

    void foo(void)
    {
       x = 0.0;
    }

    (set (reg1) (const_double (mem: "local label") xx yy))
    (set (reg2) (reg1))
    (set (mem) (reg2))

Here begins the trouble.  I can't get this optimized into
"mov const into integer reg, store into mem" or the even
more optimized zero constant case unless I have a specific
insn which performs this operation.

The crux of the problem seems to be that combine won't compress
the operations into a single op unless a specific other insn
exists to perform it.  And reload can't be expected to do it either.

This is why I have a magic pattern like this there:

(define_insn "*movsf_const_intreg"
  [(set (match_operand:SF 0 "register_operand" "=f,r")
        (match_operand:SF 1 "const_double_operand" "m#F,F"))]

This widget is the only way I could find to make the optimization
occur.

I remember now, how during my sparc backend rewrite, that I
tried to do what you are suggesting to me right now, and I ended
up with a performance regression because this const float to mem
or reg case wasn't getting optimized anymore.

I bet the above cases don't get optimized on Alpha...

Later,
David S. Miller
davem@redhat.com