This is the mail archive of the
gcc-patches@gcc.gnu.org
mailing list for the GCC project.
Re: Patch to mn10200.md to fix bad insn generation
- To: law at cygnus dot com
- Subject: Re: Patch to mn10200.md to fix bad insn generation
- From: Nick Clifton <nickc at cygnus dot com>
- Date: Mon, 29 Nov 1999 15:01:23 GMT
- CC: gcc-patches at gcc dot gnu dot org
Hi Jeff,
: So.....
:
: These addresses would have to be rejected in an operand predicate. You
: would probably need to write a new predicate since I doubt there is one
: already available that tests the conditions we want. ie
:
: blah_operand (op, mode)
: {
: return (general_operand (op, mode)
: && (GET_CODE (op) != MEM
: || memory_address_p (PSImode, XEXP (op, 0))))
: }
:
: Or something close to that. It could/should be used for both the
: patterns which optimize truncations.
Sure thing. Here is the patch. Shall I apply it this time ?
Cheers
Nick
Mon Nov 29 14:58:14 1999 Nick Clifton <nickc@cygnus.com>
* config/mn10200/mn10200.h (PREDICATE_CODES): Add
valid_psi_mode_address.
* config/mn10200/mn10200.c (valid_psi_mode_address): New
function. Return true if the operand is either a MEM valid
for a PSImode address or not a MEM at all.
* config/mn10200/mn10200.md (truncsipsi2): Use
valid_psi_mode_address.
Index: config/mn10200/mn10200.h
===================================================================
RCS file: /cvs/cvsfiles/devo/gcc/config/mn10200/mn10200.h,v
retrieving revision 1.55
diff -p -r1.55 mn10200.h
*** mn10200.h 1999/10/15 07:55:02 1.55
--- mn10200.h 1999/11/29 14:56:39
*************** do { char dstr[30]; \
*** 1063,1068 ****
--- 1063,1069 ----
#define PREDICATE_CODES \
{"call_address_operand", { SYMBOL_REF, REG }}, \
{"constant_memory_operand", { MEM }}, \
+ {"valid_psi_mode_address", { CONST_INT, MEM, REG }}, \
{"extendpsi_operand", { PLUS, CONST_INT, CONST_DOUBLE, CONST, \
SYMBOL_REF, LABEL_REF, SUBREG, REG, MEM }}, \
{"nshift_operator", { ASHIFTRT, LSHIFTRT, ASHIFT }},
Index: config/mn10200/mn10200.c
===================================================================
RCS file: /cvs/cvsfiles/devo/gcc/config/mn10200/mn10200.c,v
retrieving revision 1.41
diff -p -r1.41 mn10200.c
*** mn10200.c 1999/10/05 08:08:05 1.41
--- mn10200.c 1999/11/29 14:56:40
*************** constant_memory_operand (op, mode)
*** 875,880 ****
--- 875,892 ----
return GET_CODE (op) == MEM && CONSTANT_ADDRESS_P (XEXP (op, 0));
}
+ /* Return true if OP is a memory operand which is valid for a PSImode
+ address, or if it is not a memory operand at all. */
+ int
+ valid_psi_mode_address (op, mode)
+ rtx op;
+ enum machine_mode mode;
+ {
+ return (general_operand (op, mode)
+ && (GET_CODE (op) != MEM
+ || memory_address_p (PSImode, XEXP (op, 0))));
+ }
+
/* What (if any) secondary registers are needed to move IN with mode
MODE into a register from in register class CLASS.
Index: config/mn10200/mn10200.md
===================================================================
RCS file: /cvs/cvsfiles/devo/gcc/config/mn10200/mn10200.md,v
retrieving revision 1.64
diff -p -r1.64 mn10200.md
*** mn10200.md 1999/10/18 19:54:10 1.64
--- mn10200.md 1999/11/29 14:56:40
***************
*** 1165,1172 ****
(define_insn "truncsipsi2"
[(set (match_operand:PSI 0 "general_operand" "=a,?d,?*d,da")
! (truncate:PSI (match_operand:SI 1 "general_operand" "m,?m,?*d,i")))]
! ""
"@
mov %1,%0
movx %A1,%0
--- 1165,1172 ----
(define_insn "truncsipsi2"
[(set (match_operand:PSI 0 "general_operand" "=a,?d,?*d,da")
! (truncate:PSI (match_operand:SI 1 "valid_psi_mode_address" "m,?m,?*d,i")))]
! ""
"@
mov %1,%0
movx %A1,%0
***************
*** 1785,1791 ****
(define_insn ""
[(set (match_operand:PSI 0 "general_operand" "=d,d,a,da")
(truncate:PSI
! (ashift:SI (match_operand:SI 1 "general_operand" "d,m,m,i")
(match_operand:HI 2 "const_int_operand" "i,i,i,i"))))]
""
"*
--- 1785,1791 ----
(define_insn ""
[(set (match_operand:PSI 0 "general_operand" "=d,d,a,da")
(truncate:PSI
! (ashift:SI (match_operand:SI 1 "valid_psi_mode_address" "d,m,m,i")
(match_operand:HI 2 "const_int_operand" "i,i,i,i"))))]
""
"*