Patch: inv_reg_alloc_order

[Bernd Schmidt <bernds at pathia dot cygnus dot co dot uk>]

This patch adds a new array, inv_reg_alloc_order.  I'm going to use this in
the next version of my reload patches.  While I was there, I also made
reg_alloc_order defined for every target; if REG_ALLOC_ORDER isn't defined
it will prefer call-used regs over call-saved ones (this happens to be what
I need in the reload patch, and no other place in the compiler uses
reg_alloc_order in this case yet).

Bernd
        
	* hard-reg-set.h (reg_alloc_order): Always declare.
	(inv_reg_alloc_order): Declare.
	* regclass.c (reg_alloc_order): Always provide definition.
	(inv_reg_alloc_order): New array.
	(init_reg_sets): Initialize these arrays (if necessary).

Index: hard-reg-set.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/hard-reg-set.h,v
retrieving revision 1.4
diff -c -p -r1.4 hard-reg-set.h
*** hard-reg-set.h	1999/11/01 01:47:40	1.4
--- hard-reg-set.h	1999/11/27 13:14:01
*************** extern char global_regs[FIRST_PSEUDO_REG
*** 431,439 ****
  
  /* Table of register numbers in the order in which to try to use them.  */
  
- #ifdef REG_ALLOC_ORDER   /* Avoid undef symbol in certain broken linkers.  */
  extern int reg_alloc_order[FIRST_PSEUDO_REGISTER];
! #endif
  
  /* For each reg class, a HARD_REG_SET saying which registers are in it.  */
  
--- 431,441 ----
  
  /* Table of register numbers in the order in which to try to use them.  */
  
  extern int reg_alloc_order[FIRST_PSEUDO_REGISTER];
! 
! /* The inverse of reg_alloc_order.  */
! 
! extern int inv_reg_alloc_order[FIRST_PSEUDO_REGISTER];
  
  /* For each reg class, a HARD_REG_SET saying which registers are in it.  */
  
Index: regclass.c
===================================================================
RCS file: /cvs/gcc/egcs/gcc/regclass.c,v
retrieving revision 1.73
diff -c -p -r1.73 regclass.c
*** regclass.c	1999/11/22 14:20:35	1.73
--- regclass.c	1999/11/27 13:14:12
*************** char global_regs[FIRST_PSEUDO_REGISTER];
*** 118,125 ****
--- 118,130 ----
  /* Table of register numbers in the order in which to try to use them.  */
  #ifdef REG_ALLOC_ORDER
  int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER;
+ #else
+ int reg_alloc_order[FIRST_PSEUDO_REGISTER];
  #endif
  
+ /* The inverse of reg_alloc_order.  */
+ int inv_reg_alloc_order[FIRST_PSEUDO_REGISTER];
+ 
  /* For each reg class, a HARD_REG_SET saying which registers are in it.  */
  
  HARD_REG_SET reg_class_contents[N_REG_CLASSES];
*************** init_reg_sets ()
*** 251,256 ****
--- 256,273 ----
  
    /* Do any additional initialization regsets may need */
    INIT_ONCE_REG_SET ();
+ 
+ #ifndef REG_ALLOC_ORDER
+   for (i = j = 0; i < FIRST_PSEUDO_REGISTER; i++)
+     if (call_used_regs[i])
+       reg_alloc_order[j++] = i;
+   for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+     if (! call_used_regs[i])
+       reg_alloc_order[j++] = i;
+ #endif
+ 
+   for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+     inv_reg_alloc_order[reg_alloc_order[i]] = i;
  }
  
  /* After switches have been processed, which perhaps alter