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Re: Reload problem
- To: Joern Rennecke <amylaar at cygnus dot co dot uk>
- Subject: Re: Reload problem
- From: Andreas Schwab <schwab at suse dot de>
- Date: 09 Nov 1999 19:40:16 +0100
- Cc: gcc at gcc dot gnu dot org, gcc-patches at gnu dot org
- References: <199910261849.TAA04018@phal.cygnus.co.uk>
Joern Rennecke <amylaar@cygnus.co.uk> writes:
|> > |> What reloads do you see with this change?
|> >
|> > No reload problems as such, but completely bogus code:
|>
|> The trouble with divmodsi4 is that it is a named pattern, and hence
|> the operand numbers have to match what the rtl generation phase thinks
|> they should be.
|> This can be overcome by using a separate expander:
|>
|> (define_expand "divmodsi4"
|> [(set (match_operand:SI 0 "general_operand" "")
|> (div:SI (match_operand:SI 1 "general_operand" "")
|> (match_operand:SI 2 "general_src_operand" "")))
|> (set (match_operand:SI 3 "general_operand" "")
|> (mod:SI (match_dup 1) (match_dup 2)))]
|> "TARGET_68020 && !TARGET_5200"
|> "")
Thanks, that does help (after putting the required parallel around the
sequence). What I still wonder is why this hasn't been yet triggered on
the other architectures that have pretty much the same patterns.
Tue Nov 9 19:34:02 1999 Andreas Schwab <schwab@suse.de>
* config/m68k/m68k.md (divmodsi4, udivmodsi4, divmodhi4,
udivmodhi4): Add expanders and renumber the operands in the insn
pattern so that output operands have smaller numbers than all
input operands.
Index: m68k.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/m68k/m68k.md,v
retrieving revision 1.32
diff -u -a -u -r1.32 m68k.md
--- m68k.md 1999/10/14 17:52:48 1.32
+++ m68k.md 1999/11/09 18:32:50
@@ -3553,77 +3553,117 @@
;; Remainder instructions.
-(define_insn "divmodsi4"
+(define_expand "divmodsi4"
+ [(parallel
+ [(set (match_operand:SI 0 "general_operand" "")
+ (div:SI (match_operand:SI 1 "general_operand" "")
+ (match_operand:SI 2 "general_src_operand" "")))
+ (set (match_operand:SI 3 "general_operand" "")
+ (mod:SI (match_dup 1) (match_dup 2)))])]
+ "TARGET_68020 && !TARGET_5200"
+ "")
+
+(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=d")
- (div:SI (match_operand:SI 1 "general_operand" "0")
- (match_operand:SI 2 "general_src_operand" "dmSTK")))
- (set (match_operand:SI 3 "general_operand" "=d")
- (mod:SI (match_dup 1) (match_dup 2)))]
+ (div:SI (match_operand:SI 2 "general_operand" "0")
+ (match_operand:SI 3 "general_src_operand" "dmSTK")))
+ (set (match_operand:SI 1 "general_operand" "=d")
+ (mod:SI (match_dup 2) (match_dup 3)))]
"TARGET_68020 && !TARGET_5200"
"*
{
- if (find_reg_note (insn, REG_UNUSED, operands[3]))
- return \"divs%.l %2,%0\";
+ if (find_reg_note (insn, REG_UNUSED, operands[1]))
+ return \"divs%.l %3,%0\";
else
- return \"divsl%.l %2,%3:%0\";
+ return \"divsl%.l %3,%1:%0\";
}")
+
+(define_expand "udivmodsi4"
+ [(parallel
+ [(set (match_operand:SI 0 "general_operand" "")
+ (udiv:SI (match_operand:SI 1 "general_operand" "")
+ (match_operand:SI 2 "general_src_operand" "")))
+ (set (match_operand:SI 3 "general_operand" "")
+ (umod:SI (match_dup 1) (match_dup 2)))])]
+ "TARGET_68020 && !TARGET_5200"
+ "")
-(define_insn "udivmodsi4"
+(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=d")
- (udiv:SI (match_operand:SI 1 "general_operand" "0")
- (match_operand:SI 2 "general_src_operand" "dmSTK")))
- (set (match_operand:SI 3 "general_operand" "=d")
- (umod:SI (match_dup 1) (match_dup 2)))]
+ (udiv:SI (match_operand:SI 2 "general_operand" "0")
+ (match_operand:SI 3 "general_src_operand" "dmSTK")))
+ (set (match_operand:SI 1 "general_operand" "=d")
+ (umod:SI (match_dup 2) (match_dup 3)))]
"TARGET_68020 && !TARGET_5200"
"*
{
- if (find_reg_note (insn, REG_UNUSED, operands[3]))
- return \"divu%.l %2,%0\";
+ if (find_reg_note (insn, REG_UNUSED, operands[1]))
+ return \"divu%.l %3,%0\";
else
- return \"divul%.l %2,%3:%0\";
+ return \"divul%.l %3,%1:%0\";
}")
-(define_insn "divmodhi4"
+(define_expand "divmodhi4"
+ [(parallel
+ [(set (match_operand:HI 0 "general_operand" "")
+ (div:HI (match_operand:HI 1 "general_operand" "")
+ (match_operand:HI 2 "general_src_operand" "")))
+ (set (match_operand:HI 3 "general_operand" "")
+ (mod:HI (match_dup 1) (match_dup 2)))])]
+ "TARGET_68020 && !TARGET_5200"
+ "")
+
+(define_insn ""
[(set (match_operand:HI 0 "general_operand" "=d")
- (div:HI (match_operand:HI 1 "general_operand" "0")
- (match_operand:HI 2 "general_src_operand" "dmSKT")))
- (set (match_operand:HI 3 "general_operand" "=d")
- (mod:HI (match_dup 1) (match_dup 2)))]
+ (div:HI (match_operand:HI 2 "general_operand" "0")
+ (match_operand:HI 3 "general_src_operand" "dmSKT")))
+ (set (match_operand:HI 1 "general_operand" "=d")
+ (mod:HI (match_dup 2) (match_dup 3)))]
"!TARGET_5200"
"*
{
#ifdef MOTOROLA
- output_asm_insn (\"ext%.l %0\;divs%.w %2,%0\", operands);
+ output_asm_insn (\"ext%.l %0\;divs%.w %3,%0\", operands);
#else
- output_asm_insn (\"extl %0\;divs %2,%0\", operands);
+ output_asm_insn (\"extl %0\;divs %3,%0\", operands);
#endif
- if (!find_reg_note(insn, REG_UNUSED, operands[3]))
+ if (!find_reg_note(insn, REG_UNUSED, operands[1]))
{
CC_STATUS_INIT;
- return \"move%.l %0,%3\;swap %3\";
+ return \"move%.l %0,%1\;swap %1\";
}
else
return \"\";
}")
+
+(define_expand "udivmodhi4"
+ [(parallel
+ [(set (match_operand:HI 0 "general_operand" "")
+ (udiv:HI (match_operand:HI 1 "general_operand" "")
+ (match_operand:HI 2 "general_src_operand" "")))
+ (set (match_operand:HI 3 "general_operand" "")
+ (umod:HI (match_dup 1) (match_dup 2)))])]
+ "TARGET_68020 && !TARGET_5200"
+ "")
-(define_insn "udivmodhi4"
+(define_insn ""
[(set (match_operand:HI 0 "general_operand" "=d")
- (udiv:HI (match_operand:HI 1 "general_operand" "0")
- (match_operand:HI 2 "general_src_operand" "dmSKT")))
- (set (match_operand:HI 3 "general_operand" "=d")
- (umod:HI (match_dup 1) (match_dup 2)))]
+ (udiv:HI (match_operand:HI 2 "general_operand" "0")
+ (match_operand:HI 3 "general_src_operand" "dmSKT")))
+ (set (match_operand:HI 1 "general_operand" "=d")
+ (umod:HI (match_dup 2) (match_dup 3)))]
"!TARGET_5200"
"*
{
#ifdef MOTOROLA
- output_asm_insn (\"and%.l %#0xFFFF,%0\;divu%.w %2,%0\", operands);
+ output_asm_insn (\"and%.l %#0xFFFF,%0\;divu%.w %3,%0\", operands);
#else
- output_asm_insn (\"and%.l %#0xFFFF,%0\;divu %2,%0\", operands);
+ output_asm_insn (\"and%.l %#0xFFFF,%0\;divu %3,%0\", operands);
#endif
- if (!find_reg_note(insn, REG_UNUSED, operands[3]))
+ if (!find_reg_note(insn, REG_UNUSED, operands[1]))
{
CC_STATUS_INIT;
- return \"move%.l %0,%3\;swap %3\";
+ return \"move%.l %0,%1\;swap %1\";
}
else
return \"\";
--
Andreas Schwab "And now for something
SuSE Labs completely different."
schwab@suse.de
SuSE GmbH, Schanzäckerstr. 10, D-90443 Nürnberg