This is the mail archive of the
gcc-patches@gcc.gnu.org
mailing list for the GCC project.
*another* bug in your checkin
- To: kenner at vlsi1 dot ultra dot nyu dot edu
- Subject: *another* bug in your checkin
- From: Jeffrey A Law <law at cygnus dot com>
- Date: Mon, 01 Nov 1999 01:22:28 -0700
- Cc: gcc-patches at gcc dot gnu dot org
- Reply-To: law at cygnus dot com
The regclass.c change is causing serious problems too.
Compile this for a PA target with -O2 and look at the .lreg dump. You'll
find a pseudo is preferring SHIFT_REGS even though the pseudo is never
used in any kind of instruction that shifts a value. This causes a number
of unpleasant things to happen.
The number of problems we're finding with your checkin really worries me.
Please try to be more careful and do some testing in the future.
typedef unsigned int wint_t;
typedef unsigned int UQItype __attribute__ ((mode (QI)));
typedef int SItype __attribute__ ((mode (SI)));
typedef unsigned int USItype __attribute__ ((mode (SI)));
typedef int DItype __attribute__ ((mode (DI)));
typedef unsigned int UDItype __attribute__ ((mode (DI)));
typedef float SFtype __attribute__ ((mode (SF)));
typedef float DFtype __attribute__ ((mode (DF)));
typedef int word_type __attribute__ ((mode (__word__)));
struct DIstruct {SItype high, low;};
typedef union
{
struct DIstruct s;
DItype ll;
} DIunion;
extern DItype __fixunssfdi (SFtype a);
extern DItype __fixunsdfdi (DFtype a);
^L
static __inline__
DItype
__negdi2 (DItype u)
{
DIunion w;
DIunion uu;
w.s.high = -uu.s.high - ((USItype) w.s.low > 0);
return w.ll;
}
static __inline__
UDItype
__udivmoddi4 (UDItype n, UDItype d, UDItype *rp)
{
DIunion ww;
DIunion nn, dd;
DIunion rr;
USItype d0, d1, n0, n1, n2;
USItype q0, q1;
USItype b, bm;
dd.ll = d;
d0 = dd.s.low;
if (d0 > n1)
{
USItype __tmp;
__asm__ ("" : "=r" ( bm ), "=r" (__tmp) : "1" ( d0 ));
d0 = d0 << bm;
}
}
DItype
__divdi3 (DItype u, DItype v)
{
DIunion uu, vv;
vv.ll = __negdi2 (vv.ll);
__udivmoddi4 (uu.ll, vv.ll, (UDItype *) 0);
}