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MIPS PATCH: ISA_HAS_xxx
- To: <gcc-patches at gcc dot gnu dot org>
- Subject: MIPS PATCH: ISA_HAS_xxx
- From: Gavin Romig-Koch <gavin at cygnus dot com>
- Date: Tue, 26 Oct 1999 15:54:45 -0400 (EDT)
I've just commited the following.
-gavin...
* config/mips/mips.h (ISA_HAS_64BIT_REGS,ISA_HAS_BRANCHLIKELY,
ISA_HAS_FP4,ISA_HAS_CONDMOVE): New.
(GENERATE_BRANCHLIKELY,HAVE_SQRT_P,
CONDITIONAL_REGISTER_USEAGE): Use them.
* config/mips/mips.c (mips_move_1word,mips_move_2words,
gen_conditional_branch,override_options) : Use them.
* config/mips/mips.md : Use them.
Index: mips.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/mips/mips.h,v
retrieving revision 1.73
diff -c -p -r1.73 mips.h
*** mips.h 1999/10/25 21:44:39 1.73
--- mips.h 1999/10/26 18:52:58
*************** extern void sbss_section PARAMS ((void)
*** 542,548 ****
/* This is meant to be redefined in the host dependent files. */
#define SUBTARGET_TARGET_OPTIONS
! #define GENERATE_BRANCHLIKELY (!TARGET_MIPS16 && (TARGET_MIPS3900 || (mips_isa >= 2)))
/* Generate three-operand multiply instructions for both SImode and DImode. */
#define GENERATE_MULT3 (TARGET_MIPS3900 \
--- 542,548 ----
/* This is meant to be redefined in the host dependent files. */
#define SUBTARGET_TARGET_OPTIONS
! #define GENERATE_BRANCHLIKELY (!TARGET_MIPS16 && (TARGET_MIPS3900 || ISA_HAS_BRANCHLIKELY))
/* Generate three-operand multiply instructions for both SImode and DImode. */
#define GENERATE_MULT3 (TARGET_MIPS3900 \
*************** extern void sbss_section PARAMS ((void)
*** 552,559 ****
depending on the instruction set architecture level. */
#define BRANCH_LIKELY_P() GENERATE_BRANCHLIKELY
! #define HAVE_SQRT_P() (mips_isa >= 2)
/* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
-mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
-mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in
--- 552,571 ----
depending on the instruction set architecture level. */
#define BRANCH_LIKELY_P() GENERATE_BRANCHLIKELY
! #define HAVE_SQRT_P() (mips_isa != 1)
+ /* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
+ #define ISA_HAS_64BIT_REGS (mips_isa == 3 || mips_isa == 4 || mips_isa == 64)
+
+ /* ISA has branch likely instructions (eg. mips2). */
+ #define ISA_HAS_BRANCHLIKELY (mips_isa != 1)
+
+ /* ISA has the FP instructions introduced in mips4. */
+ #define ISA_HAS_FP4 (mips_isa == 4)
+
+ /* ISA has the non-FP conditional move instructions introduced in mips4. */
+ #define ISA_HAS_CONDMOVE (mips_isa == 4)
+
/* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
-mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
-mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in
*************** do \
*** 622,628 ****
for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
fixed_regs[regno] = call_used_regs[regno] = 1; \
} \
! else if (mips_isa < 4) \
{ \
int regno; \
\
--- 634,640 ----
for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
fixed_regs[regno] = call_used_regs[regno] = 1; \
} \
! else if (! ISA_HAS_FP4) \
{ \
int regno; \
\
Index: mips.c
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/mips/mips.c,v
retrieving revision 1.76
diff -c -p -r1.76 mips.c
*** mips.c 1999/10/25 21:44:39 1.76
--- mips.c 1999/10/26 18:53:08
*************** mips_move_1word (operands, insn, unsigne
*** 1719,1725 ****
ret = "mflo\t%0";
}
! else if (ST_REG_P (regno1) && mips_isa >= 4)
ret = "li\t%0,1\n\tmovf\t%0,%.,%1";
else
--- 1719,1725 ----
ret = "mflo\t%0";
}
! else if (ST_REG_P (regno1) && ISA_HAS_FP4)
ret = "li\t%0,1\n\tmovf\t%0,%.,%1";
else
*************** mips_move_1word (operands, insn, unsigne
*** 1728,1734 ****
if (FP_REG_P (regno1))
ret = "mfc1\t%0,%1";
! else if (regno1 == FPSW_REGNUM && mips_isa < 4)
ret = "cfc1\t%0,$31";
}
}
--- 1728,1734 ----
if (FP_REG_P (regno1))
ret = "mfc1\t%0,%1";
! else if (regno1 == FPSW_REGNUM && ! ISA_HAS_FP4)
ret = "cfc1\t%0,$31";
}
}
*************** mips_move_1word (operands, insn, unsigne
*** 1755,1761 ****
}
}
! else if (regno0 == FPSW_REGNUM && mips_isa < 4)
{
if (GP_REG_P (regno1))
{
--- 1755,1761 ----
}
}
! else if (regno0 == FPSW_REGNUM && ! ISA_HAS_FP4)
{
if (GP_REG_P (regno1))
{
*************** mips_move_2words (operands, insn)
*** 2218,2224 ****
or higher. For !TARGET_64BIT && gp registers we
need to avoid this by using two li instructions
instead. */
! if (mips_isa >= 3 && !TARGET_64BIT && !FP_REG_P (regno0))
{
split_double (op1, operands + 2, operands + 3);
ret = "li\t%0,%2\n\tli\t%D0,%3";
--- 2218,2226 ----
or higher. For !TARGET_64BIT && gp registers we
need to avoid this by using two li instructions
instead. */
! if (ISA_HAS_64BIT_REGS
! && ! TARGET_64BIT
! && ! FP_REG_P (regno0))
{
split_double (op1, operands + 2, operands + 3);
ret = "li\t%0,%2\n\tli\t%D0,%3";
*************** gen_conditional_branch (operands, test_c
*** 2871,2877 ****
case CMP_SF:
case CMP_DF:
! if (mips_isa < 4)
reg = gen_rtx_REG (CCmode, FPSW_REGNUM);
else
reg = gen_reg_rtx (CCmode);
--- 2873,2879 ----
case CMP_SF:
case CMP_DF:
! if (! ISA_HAS_FP4)
reg = gen_rtx_REG (CCmode, FPSW_REGNUM);
else
reg = gen_reg_rtx (CCmode);
*************** override_options ()
*** 4363,4369 ****
if (mips_abi_string == 0 && mips_isa_string
&& mips_abi != ABI_EABI && mips_abi != ABI_O64)
{
! if (mips_isa <= 2)
mips_abi = ABI_32;
else
mips_abi = ABI_64;
--- 4365,4371 ----
if (mips_abi_string == 0 && mips_isa_string
&& mips_abi != ABI_EABI && mips_abi != ABI_O64)
{
! if (! ISA_HAS_64BIT_REGS)
mips_abi = ABI_32;
else
mips_abi = ABI_64;
*************** override_options ()
*** 4384,4392 ****
/* If both ABI and ISA were specified, check for conflicts. */
else if (mips_isa_string && mips_abi_string)
{
! if ((mips_isa <= 2 && (mips_abi == ABI_N32 || mips_abi == ABI_64
|| mips_abi == ABI_O64))
! || (mips_isa >= 3 && mips_abi == ABI_32))
error ("-mabi=%s does not support -mips%d", mips_abi_string, mips_isa);
}
--- 4386,4394 ----
/* If both ABI and ISA were specified, check for conflicts. */
else if (mips_isa_string && mips_abi_string)
{
! if ((! ISA_HAS_64BIT_REGS && (mips_abi == ABI_N32 || mips_abi == ABI_64
|| mips_abi == ABI_O64))
! || (ISA_HAS_64BIT_REGS && mips_abi == ABI_32))
error ("-mabi=%s does not support -mips%d", mips_abi_string, mips_isa);
}
*************** override_options ()
*** 4535,4558 ****
}
}
! if ((mips_cpu == PROCESSOR_R3000 && mips_isa > 1)
! || (mips_cpu == PROCESSOR_R6000 && mips_isa > 2)
|| ((mips_cpu == PROCESSOR_R4000
|| mips_cpu == PROCESSOR_R4100
|| mips_cpu == PROCESSOR_R4300
|| mips_cpu == PROCESSOR_R4600
|| mips_cpu == PROCESSOR_R4650)
! && mips_isa > 3))
error ("-mcpu=%s does not support -mips%d", mips_cpu_string, mips_isa);
/* make sure sizes of ints/longs/etc. are ok */
! if (mips_isa < 3)
{
if (TARGET_FLOAT64)
! fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit fp registers");
else if (TARGET_64BIT)
! fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit gp registers");
}
if (mips_abi != ABI_32 && mips_abi != ABI_O64)
--- 4537,4560 ----
}
}
! if ((mips_cpu == PROCESSOR_R3000 && (mips_isa != 1))
! || (mips_cpu == PROCESSOR_R6000 && mips_isa != 1 && mips_isa != 2)
|| ((mips_cpu == PROCESSOR_R4000
|| mips_cpu == PROCESSOR_R4100
|| mips_cpu == PROCESSOR_R4300
|| mips_cpu == PROCESSOR_R4600
|| mips_cpu == PROCESSOR_R4650)
! && mips_isa != 1 && mips_isa != 2 && mips_isa != 3))
error ("-mcpu=%s does not support -mips%d", mips_cpu_string, mips_isa);
/* make sure sizes of ints/longs/etc. are ok */
! if (! ISA_HAS_64BIT_REGS)
{
if (TARGET_FLOAT64)
! fatal ("-mips%d does not support 64 bit fp registers", mips_isa);
else if (TARGET_64BIT)
! fatal ("-mips%d does not support 64 bit gp registers", mips_isa);
}
if (mips_abi != ABI_32 && mips_abi != ABI_O64)
*************** override_options ()
*** 4731,4737 ****
if (mode == CCmode)
{
! if (mips_isa < 4)
temp = (regno == FPSW_REGNUM);
else
temp = (ST_REG_P (regno) || GP_REG_P (regno)
--- 4733,4739 ----
if (mode == CCmode)
{
! if (! ISA_HAS_FP4)
temp = (regno == FPSW_REGNUM);
else
temp = (ST_REG_P (regno) || GP_REG_P (regno)
Index: mips.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/mips/mips.md,v
retrieving revision 1.68
diff -c -p -r1.68 mips.md
*** mips.md 1999/10/20 18:29:09 1.68
--- mips.md 1999/10/26 18:54:04
***************
*** 2075,2081 ****
(plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
(match_operand:DF 2 "register_operand" "f"))
(match_operand:DF 3 "register_operand" "f")))]
! "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"madd.d\\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "mode" "DF")])
--- 2075,2081 ----
(plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
(match_operand:DF 2 "register_operand" "f"))
(match_operand:DF 3 "register_operand" "f")))]
! "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"madd.d\\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "mode" "DF")])
***************
*** 2085,2091 ****
(plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f"))
(match_operand:SF 3 "register_operand" "f")))]
! "mips_isa >= 4 && TARGET_HARD_FLOAT"
"madd.s\\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "mode" "SF")])
--- 2085,2091 ----
(plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f"))
(match_operand:SF 3 "register_operand" "f")))]
! "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"madd.s\\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "mode" "SF")])
***************
*** 2095,2101 ****
(minus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
(match_operand:DF 2 "register_operand" "f"))
(match_operand:DF 3 "register_operand" "f")))]
! "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"msub.d\\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "mode" "DF")])
--- 2095,2101 ----
(minus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
(match_operand:DF 2 "register_operand" "f"))
(match_operand:DF 3 "register_operand" "f")))]
! "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"msub.d\\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "mode" "DF")])
***************
*** 2106,2112 ****
(match_operand:SF 2 "register_operand" "f"))
(match_operand:SF 3 "register_operand" "f")))]
! "mips_isa >= 4 && TARGET_HARD_FLOAT"
"msub.s\\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "mode" "SF")])
--- 2106,2112 ----
(match_operand:SF 2 "register_operand" "f"))
(match_operand:SF 3 "register_operand" "f")))]
! "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"msub.s\\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "mode" "SF")])
***************
*** 2116,2122 ****
(neg:DF (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
(match_operand:DF 2 "register_operand" "f"))
(match_operand:DF 3 "register_operand" "f"))))]
! "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"nmadd.d\\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "mode" "DF")])
--- 2116,2122 ----
(neg:DF (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
(match_operand:DF 2 "register_operand" "f"))
(match_operand:DF 3 "register_operand" "f"))))]
! "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"nmadd.d\\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "mode" "DF")])
***************
*** 2126,2132 ****
(neg:SF (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f"))
(match_operand:SF 3 "register_operand" "f"))))]
! "mips_isa >= 4 && TARGET_HARD_FLOAT"
"nmadd.s\\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "mode" "SF")])
--- 2126,2132 ----
(neg:SF (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f"))
(match_operand:SF 3 "register_operand" "f"))))]
! "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"nmadd.s\\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "mode" "SF")])
***************
*** 2136,2142 ****
(minus:DF (match_operand:DF 1 "register_operand" "f")
(mult:DF (match_operand:DF 2 "register_operand" "f")
(match_operand:DF 3 "register_operand" "f"))))]
! "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"nmsub.d\\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
(set_attr "mode" "DF")])
--- 2136,2142 ----
(minus:DF (match_operand:DF 1 "register_operand" "f")
(mult:DF (match_operand:DF 2 "register_operand" "f")
(match_operand:DF 3 "register_operand" "f"))))]
! "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"nmsub.d\\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
(set_attr "mode" "DF")])
***************
*** 2146,2152 ****
(minus:SF (match_operand:SF 1 "register_operand" "f")
(mult:SF (match_operand:SF 2 "register_operand" "f")
(match_operand:SF 3 "register_operand" "f"))))]
! "mips_isa >= 4 && TARGET_HARD_FLOAT"
"nmsub.s\\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
(set_attr "mode" "SF")])
--- 2146,2152 ----
(minus:SF (match_operand:SF 1 "register_operand" "f")
(mult:SF (match_operand:SF 2 "register_operand" "f")
(match_operand:SF 3 "register_operand" "f"))))]
! "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"nmsub.s\\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
(set_attr "mode" "SF")])
***************
*** 2181,2187 ****
[(set (match_operand:DF 0 "register_operand" "=f")
(div:DF (match_operand:DF 1 "const_float_1_operand" "")
(match_operand:DF 2 "register_operand" "f")))]
! "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && flag_fast_math"
"recip.d\\t%0,%2"
[(set_attr "type" "fdiv")
(set_attr "mode" "DF")])
--- 2181,2187 ----
[(set (match_operand:DF 0 "register_operand" "=f")
(div:DF (match_operand:DF 1 "const_float_1_operand" "")
(match_operand:DF 2 "register_operand" "f")))]
! "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && flag_fast_math"
"recip.d\\t%0,%2"
[(set_attr "type" "fdiv")
(set_attr "mode" "DF")])
***************
*** 2190,2196 ****
[(set (match_operand:SF 0 "register_operand" "=f")
(div:SF (match_operand:SF 1 "const_float_1_operand" "")
(match_operand:SF 2 "register_operand" "f")))]
! "mips_isa >= 4 && TARGET_HARD_FLOAT && flag_fast_math"
"recip.s\\t%0,%2"
[(set_attr "type" "fdiv")
(set_attr "mode" "SF")])
--- 2190,2196 ----
[(set (match_operand:SF 0 "register_operand" "=f")
(div:SF (match_operand:SF 1 "const_float_1_operand" "")
(match_operand:SF 2 "register_operand" "f")))]
! "ISA_HAS_FP4 && TARGET_HARD_FLOAT && flag_fast_math"
"recip.s\\t%0,%2"
[(set_attr "type" "fdiv")
(set_attr "mode" "SF")])
***************
*** 2782,2788 ****
[(set (match_operand:DF 0 "register_operand" "=f")
(div:DF (match_operand:DF 1 "const_float_1_operand" "")
(sqrt:DF (match_operand:DF 2 "register_operand" "f"))))]
! "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && flag_fast_math"
"rsqrt.d\\t%0,%2"
[(set_attr "type" "fsqrt")
(set_attr "mode" "DF")])
--- 2782,2788 ----
[(set (match_operand:DF 0 "register_operand" "=f")
(div:DF (match_operand:DF 1 "const_float_1_operand" "")
(sqrt:DF (match_operand:DF 2 "register_operand" "f"))))]
! "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && flag_fast_math"
"rsqrt.d\\t%0,%2"
[(set_attr "type" "fsqrt")
(set_attr "mode" "DF")])
***************
*** 2791,2797 ****
[(set (match_operand:SF 0 "register_operand" "=f")
(div:SF (match_operand:SF 1 "const_float_1_operand" "")
(sqrt:SF (match_operand:SF 2 "register_operand" "f"))))]
! "mips_isa >= 4 && TARGET_HARD_FLOAT && flag_fast_math"
"rsqrt.s\\t%0,%2"
[(set_attr "type" "fsqrt")
(set_attr "mode" "SF")])
--- 2791,2797 ----
[(set (match_operand:SF 0 "register_operand" "=f")
(div:SF (match_operand:SF 1 "const_float_1_operand" "")
(sqrt:SF (match_operand:SF 2 "register_operand" "f"))))]
! "ISA_HAS_FP4 && TARGET_HARD_FLOAT && flag_fast_math"
"rsqrt.s\\t%0,%2"
[(set_attr "type" "fsqrt")
(set_attr "mode" "SF")])
*************** move\\t%0,%z4\\n\\
*** 5565,5571 ****
(define_insn "movcc"
[(set (match_operand:CC 0 "nonimmediate_operand" "=d,*d,*d,*d,*R,*m,*d,*f,*f,*f,*f,*R,*m")
(match_operand:CC 1 "general_operand" "z,*d,*R,*m,*d,*d,*f,*d,*f,*R,*m,*f,*f"))]
! "mips_isa >= 4 && TARGET_HARD_FLOAT"
"* return mips_move_1word (operands, insn, FALSE);"
[(set_attr "type" "move,move,load,load,store,store,xfer,xfer,move,load,load,store,store")
(set_attr "mode" "SI")
--- 5565,5571 ----
(define_insn "movcc"
[(set (match_operand:CC 0 "nonimmediate_operand" "=d,*d,*d,*d,*R,*m,*d,*f,*f,*f,*f,*R,*m")
(match_operand:CC 1 "general_operand" "z,*d,*R,*m,*d,*d,*f,*d,*f,*R,*m,*f,*f"))]
! "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"* return mips_move_1word (operands, insn, FALSE);"
[(set_attr "type" "move,move,load,load,store,store,xfer,xfer,move,load,load,store,store")
(set_attr "mode" "SI")
*************** move\\t%0,%z4\\n\\
*** 5577,5583 ****
[(set (match_operand:CC 0 "register_operand" "=z")
(match_operand:CC 1 "general_operand" "z"))
(clobber (match_operand:TF 2 "register_operand" "=&f"))]
! "mips_isa >= 4 && TARGET_HARD_FLOAT"
"
{
rtx source;
--- 5577,5583 ----
[(set (match_operand:CC 0 "register_operand" "=z")
(match_operand:CC 1 "general_operand" "z"))
(clobber (match_operand:TF 2 "register_operand" "=&f"))]
! "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"
{
rtx source;
*************** move\\t%0,%z4\\n\\
*** 5615,5621 ****
[(set (match_operand:CC 0 "general_operand" "=z")
(match_operand:CC 1 "register_operand" "z"))
(clobber (match_operand:CC 2 "register_operand" "=&d"))]
! "mips_isa >= 4 && TARGET_HARD_FLOAT"
"
{
/* This is called when we are copying a condition code register out
--- 5615,5621 ----
[(set (match_operand:CC 0 "general_operand" "=z")
(match_operand:CC 1 "register_operand" "z"))
(clobber (match_operand:CC 2 "register_operand" "=&d"))]
! "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"
{
/* This is called when we are copying a condition code register out
*************** move\\t%0,%z4\\n\\
*** 5657,5663 ****
[(set (match_operand:SF 0 "register_operand" "=f")
(mem:SF (plus:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "register_operand" "d"))))]
! "mips_isa >= 4 && TARGET_HARD_FLOAT"
"lwxc1\\t%0,%1(%2)"
[(set_attr "type" "load")
(set_attr "mode" "SF")])
--- 5657,5663 ----
[(set (match_operand:SF 0 "register_operand" "=f")
(mem:SF (plus:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "register_operand" "d"))))]
! "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"lwxc1\\t%0,%1(%2)"
[(set_attr "type" "load")
(set_attr "mode" "SF")])
*************** move\\t%0,%z4\\n\\
*** 5666,5672 ****
[(set (match_operand:SF 0 "register_operand" "=f")
(mem:SF (plus:DI (match_operand:DI 1 "se_register_operand" "d")
(match_operand:DI 2 "se_register_operand" "d"))))]
! "mips_isa >= 4 && TARGET_HARD_FLOAT"
"lwxc1\\t%0,%1(%2)"
[(set_attr "type" "load")
(set_attr "mode" "SF")])
--- 5666,5672 ----
[(set (match_operand:SF 0 "register_operand" "=f")
(mem:SF (plus:DI (match_operand:DI 1 "se_register_operand" "d")
(match_operand:DI 2 "se_register_operand" "d"))))]
! "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"lwxc1\\t%0,%1(%2)"
[(set_attr "type" "load")
(set_attr "mode" "SF")])
*************** move\\t%0,%z4\\n\\
*** 5675,5681 ****
[(set (match_operand:DF 0 "register_operand" "=f")
(mem:DF (plus:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "register_operand" "d"))))]
! "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"ldxc1\\t%0,%1(%2)"
[(set_attr "type" "load")
(set_attr "mode" "DF")])
--- 5675,5681 ----
[(set (match_operand:DF 0 "register_operand" "=f")
(mem:DF (plus:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "register_operand" "d"))))]
! "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"ldxc1\\t%0,%1(%2)"
[(set_attr "type" "load")
(set_attr "mode" "DF")])
*************** move\\t%0,%z4\\n\\
*** 5684,5690 ****
[(set (match_operand:DF 0 "register_operand" "=f")
(mem:DF (plus:DI (match_operand:DI 1 "se_register_operand" "d")
(match_operand:DI 2 "se_register_operand" "d"))))]
! "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"ldxc1\\t%0,%1(%2)"
[(set_attr "type" "load")
(set_attr "mode" "DF")])
--- 5684,5690 ----
[(set (match_operand:DF 0 "register_operand" "=f")
(mem:DF (plus:DI (match_operand:DI 1 "se_register_operand" "d")
(match_operand:DI 2 "se_register_operand" "d"))))]
! "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"ldxc1\\t%0,%1(%2)"
[(set_attr "type" "load")
(set_attr "mode" "DF")])
*************** move\\t%0,%z4\\n\\
*** 5693,5699 ****
[(set (mem:SF (plus:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "register_operand" "d")))
(match_operand:SF 0 "register_operand" "f"))]
! "mips_isa >= 4 && TARGET_HARD_FLOAT"
"swxc1\\t%0,%1(%2)"
[(set_attr "type" "store")
(set_attr "mode" "SF")])
--- 5693,5699 ----
[(set (mem:SF (plus:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "register_operand" "d")))
(match_operand:SF 0 "register_operand" "f"))]
! "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"swxc1\\t%0,%1(%2)"
[(set_attr "type" "store")
(set_attr "mode" "SF")])
*************** move\\t%0,%z4\\n\\
*** 5702,5708 ****
[(set (mem:SF (plus:DI (match_operand:DI 1 "se_register_operand" "d")
(match_operand:DI 2 "se_register_operand" "d")))
(match_operand:SF 0 "register_operand" "f"))]
! "mips_isa >= 4 && TARGET_HARD_FLOAT"
"swxc1\\t%0,%1(%2)"
[(set_attr "type" "store")
(set_attr "mode" "SF")])
--- 5702,5708 ----
[(set (mem:SF (plus:DI (match_operand:DI 1 "se_register_operand" "d")
(match_operand:DI 2 "se_register_operand" "d")))
(match_operand:SF 0 "register_operand" "f"))]
! "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"swxc1\\t%0,%1(%2)"
[(set_attr "type" "store")
(set_attr "mode" "SF")])
*************** move\\t%0,%z4\\n\\
*** 5711,5717 ****
[(set (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "register_operand" "d")))
(match_operand:DF 0 "register_operand" "f"))]
! "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"sdxc1\\t%0,%1(%2)"
[(set_attr "type" "store")
(set_attr "mode" "DF")])
--- 5711,5717 ----
[(set (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "register_operand" "d")))
(match_operand:DF 0 "register_operand" "f"))]
! "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"sdxc1\\t%0,%1(%2)"
[(set_attr "type" "store")
(set_attr "mode" "DF")])
*************** move\\t%0,%z4\\n\\
*** 5720,5726 ****
[(set (mem:DF (plus:DI (match_operand:DI 1 "se_register_operand" "d")
(match_operand:DI 2 "se_register_operand" "d")))
(match_operand:DF 0 "register_operand" "f"))]
! "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"sdxc1\\t%0,%1(%2)"
[(set_attr "type" "store")
(set_attr "mode" "DF")])
--- 5720,5726 ----
[(set (mem:DF (plus:DI (match_operand:DI 1 "se_register_operand" "d")
(match_operand:DI 2 "se_register_operand" "d")))
(match_operand:DF 0 "register_operand" "f"))]
! "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"sdxc1\\t%0,%1(%2)"
[(set_attr "type" "store")
(set_attr "mode" "DF")])
*************** lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\
*** 9924,9930 ****
(const_int 0)])
(match_operand:SI 2 "reg_or_0_operand" "dJ,0")
(match_operand:SI 3 "reg_or_0_operand" "0,dJ")))]
! "mips_isa >= 4"
"@
mov%B4\\t%0,%z2,%1
mov%b4\\t%0,%z3,%1"
--- 9924,9930 ----
(const_int 0)])
(match_operand:SI 2 "reg_or_0_operand" "dJ,0")
(match_operand:SI 3 "reg_or_0_operand" "0,dJ")))]
! "ISA_HAS_CONDMOVE"
"@
mov%B4\\t%0,%z2,%1
mov%b4\\t%0,%z3,%1"
*************** lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\
*** 9939,9945 ****
(const_int 0)])
(match_operand:SI 2 "reg_or_0_operand" "dJ,0")
(match_operand:SI 3 "reg_or_0_operand" "0,dJ")))]
! "mips_isa >= 4"
"@
mov%B4\\t%0,%z2,%1
mov%b4\\t%0,%z3,%1"
--- 9939,9945 ----
(const_int 0)])
(match_operand:SI 2 "reg_or_0_operand" "dJ,0")
(match_operand:SI 3 "reg_or_0_operand" "0,dJ")))]
! "ISA_HAS_CONDMOVE"
"@
mov%B4\\t%0,%z2,%1
mov%b4\\t%0,%z3,%1"
*************** lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\
*** 9955,9961 ****
(const_int 0)])
(match_operand:SI 1 "reg_or_0_operand" "dJ,0")
(match_operand:SI 2 "reg_or_0_operand" "0,dJ")))]
! "mips_isa >= 4 && TARGET_HARD_FLOAT"
"@
mov%T3\\t%0,%z1,%4
mov%t3\\t%0,%z2,%4"
--- 9955,9961 ----
(const_int 0)])
(match_operand:SI 1 "reg_or_0_operand" "dJ,0")
(match_operand:SI 2 "reg_or_0_operand" "0,dJ")))]
! "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"@
mov%T3\\t%0,%z1,%4
mov%t3\\t%0,%z2,%4"
*************** lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\
*** 9970,9976 ****
(const_int 0)])
(match_operand:DI 2 "se_reg_or_0_operand" "dJ,0")
(match_operand:DI 3 "se_reg_or_0_operand" "0,dJ")))]
! "mips_isa >= 4"
"@
mov%B4\\t%0,%z2,%1
mov%b4\\t%0,%z3,%1"
--- 9970,9976 ----
(const_int 0)])
(match_operand:DI 2 "se_reg_or_0_operand" "dJ,0")
(match_operand:DI 3 "se_reg_or_0_operand" "0,dJ")))]
! "ISA_HAS_CONDMOVE"
"@
mov%B4\\t%0,%z2,%1
mov%b4\\t%0,%z3,%1"
*************** lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\
*** 9985,9991 ****
(const_int 0)])
(match_operand:DI 2 "se_reg_or_0_operand" "dJ,0")
(match_operand:DI 3 "se_reg_or_0_operand" "0,dJ")))]
! "mips_isa >= 4"
"@
mov%B4\\t%0,%z2,%1
mov%b4\\t%0,%z3,%1"
--- 9985,9991 ----
(const_int 0)])
(match_operand:DI 2 "se_reg_or_0_operand" "dJ,0")
(match_operand:DI 3 "se_reg_or_0_operand" "0,dJ")))]
! "ISA_HAS_CONDMOVE"
"@
mov%B4\\t%0,%z2,%1
mov%b4\\t%0,%z3,%1"
*************** lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\
*** 10001,10007 ****
(const_int 0)])
(match_operand:DI 1 "se_reg_or_0_operand" "dJ,0")
(match_operand:DI 2 "se_reg_or_0_operand" "0,dJ")))]
! "mips_isa >= 4 && TARGET_HARD_FLOAT"
"@
mov%T3\\t%0,%z1,%4
mov%t3\\t%0,%z2,%4"
--- 10001,10007 ----
(const_int 0)])
(match_operand:DI 1 "se_reg_or_0_operand" "dJ,0")
(match_operand:DI 2 "se_reg_or_0_operand" "0,dJ")))]
! "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"@
mov%T3\\t%0,%z1,%4
mov%t3\\t%0,%z2,%4"
*************** lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\
*** 10016,10022 ****
(const_int 0)])
(match_operand:SF 2 "register_operand" "f,0")
(match_operand:SF 3 "register_operand" "0,f")))]
! "mips_isa >= 4 && TARGET_HARD_FLOAT"
"@
mov%B4.s\\t%0,%2,%1
mov%b4.s\\t%0,%3,%1"
--- 10016,10022 ----
(const_int 0)])
(match_operand:SF 2 "register_operand" "f,0")
(match_operand:SF 3 "register_operand" "0,f")))]
! "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"@
mov%B4.s\\t%0,%2,%1
mov%b4.s\\t%0,%3,%1"
*************** lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\
*** 10031,10037 ****
(const_int 0)])
(match_operand:SF 2 "register_operand" "f,0")
(match_operand:SF 3 "register_operand" "0,f")))]
! "mips_isa >= 4 && TARGET_HARD_FLOAT"
"@
mov%B4.s\\t%0,%2,%1
mov%b4.s\\t%0,%3,%1"
--- 10031,10037 ----
(const_int 0)])
(match_operand:SF 2 "register_operand" "f,0")
(match_operand:SF 3 "register_operand" "0,f")))]
! "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"@
mov%B4.s\\t%0,%2,%1
mov%b4.s\\t%0,%3,%1"
*************** lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\
*** 10047,10053 ****
(const_int 0)])
(match_operand:SF 1 "register_operand" "f,0")
(match_operand:SF 2 "register_operand" "0,f")))]
! "mips_isa >= 4 && TARGET_HARD_FLOAT"
"@
mov%T3.s\\t%0,%1,%4
mov%t3.s\\t%0,%2,%4"
--- 10047,10053 ----
(const_int 0)])
(match_operand:SF 1 "register_operand" "f,0")
(match_operand:SF 2 "register_operand" "0,f")))]
! "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"@
mov%T3.s\\t%0,%1,%4
mov%t3.s\\t%0,%2,%4"
*************** lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\
*** 10062,10068 ****
(const_int 0)])
(match_operand:DF 2 "register_operand" "f,0")
(match_operand:DF 3 "register_operand" "0,f")))]
! "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"@
mov%B4.d\\t%0,%2,%1
mov%b4.d\\t%0,%3,%1"
--- 10062,10068 ----
(const_int 0)])
(match_operand:DF 2 "register_operand" "f,0")
(match_operand:DF 3 "register_operand" "0,f")))]
! "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"@
mov%B4.d\\t%0,%2,%1
mov%b4.d\\t%0,%3,%1"
*************** lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\
*** 10077,10083 ****
(const_int 0)])
(match_operand:DF 2 "register_operand" "f,0")
(match_operand:DF 3 "register_operand" "0,f")))]
! "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"@
mov%B4.d\\t%0,%2,%1
mov%b4.d\\t%0,%3,%1"
--- 10077,10083 ----
(const_int 0)])
(match_operand:DF 2 "register_operand" "f,0")
(match_operand:DF 3 "register_operand" "0,f")))]
! "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"@
mov%B4.d\\t%0,%2,%1
mov%b4.d\\t%0,%3,%1"
*************** lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\
*** 10093,10099 ****
(const_int 0)])
(match_operand:DF 1 "register_operand" "f,0")
(match_operand:DF 2 "register_operand" "0,f")))]
! "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"@
mov%T3.d\\t%0,%1,%4
mov%t3.d\\t%0,%2,%4"
--- 10093,10099 ----
(const_int 0)])
(match_operand:DF 1 "register_operand" "f,0")
(match_operand:DF 2 "register_operand" "0,f")))]
! "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"@
mov%T3.d\\t%0,%1,%4
mov%t3.d\\t%0,%2,%4"
*************** lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\
*** 10108,10114 ****
(if_then_else:SI (match_dup 5)
(match_operand:SI 2 "reg_or_0_operand" "")
(match_operand:SI 3 "reg_or_0_operand" "")))]
! "mips_isa >= 4"
"
{
gen_conditional_move (operands);
--- 10108,10114 ----
(if_then_else:SI (match_dup 5)
(match_operand:SI 2 "reg_or_0_operand" "")
(match_operand:SI 3 "reg_or_0_operand" "")))]
! "ISA_HAS_CONDMOVE || ISA_HAS_FP4"
"
{
gen_conditional_move (operands);
*************** lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\
*** 10121,10127 ****
(if_then_else:DI (match_dup 5)
(match_operand:DI 2 "se_reg_or_0_operand" "")
(match_operand:DI 3 "se_reg_or_0_operand" "")))]
! "mips_isa >= 4"
"
{
gen_conditional_move (operands);
--- 10121,10127 ----
(if_then_else:DI (match_dup 5)
(match_operand:DI 2 "se_reg_or_0_operand" "")
(match_operand:DI 3 "se_reg_or_0_operand" "")))]
! "ISA_HAS_CONDMOVE || ISA_HAS_FP4"
"
{
gen_conditional_move (operands);
*************** lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\
*** 10134,10140 ****
(if_then_else:SF (match_dup 5)
(match_operand:SF 2 "register_operand" "")
(match_operand:SF 3 "register_operand" "")))]
! "mips_isa >= 4 && TARGET_HARD_FLOAT"
"
{
gen_conditional_move (operands);
--- 10134,10140 ----
(if_then_else:SF (match_dup 5)
(match_operand:SF 2 "register_operand" "")
(match_operand:SF 3 "register_operand" "")))]
! "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"
{
gen_conditional_move (operands);
*************** lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\
*** 10147,10153 ****
(if_then_else:DF (match_dup 5)
(match_operand:DF 2 "register_operand" "")
(match_operand:DF 3 "register_operand" "")))]
! "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"
{
gen_conditional_move (operands);
--- 10147,10153 ----
(if_then_else:DF (match_dup 5)
(match_operand:DF 2 "register_operand" "")
(match_operand:DF 3 "register_operand" "")))]
! "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"
{
gen_conditional_move (operands);