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Patch for --enable-checking ICE in div_trap on mips.
- To: gcc-patches at gcc dot gnu dot org, gavin at cygnus dot com
- Subject: Patch for --enable-checking ICE in div_trap on mips.
- From: Geoff Keating <geoffk at ozemail dot com dot au>
- Date: Sun, 10 Oct 1999 17:07:23 +1000
This fixes an --enable-checking failure on MIPS. I _think_ this is
what the code was trying to do.
OK to commit?
--
Geoffrey Keating <geoffk@cygnus.com>
===File ~/patches/cygnus/tx49-egcs-divtrap.patch============
md5sum: 3fe0bd7ce737a285 7bb662d57288fd84 324913
Index: egcs/gcc/ChangeLog
0a
Sat Oct 9 17:05:32 1999 Geoffrey Keating <geoffk@cygnus.com>
* config/mips/mips.md (div_trap_normal): Don't ask for the REGNO
of (const_int 0), when what we really care about is
whether it's a zero constant anyway.
(div_trap_mips16): Likewise.
.
Changed files:
egcs/gcc/ChangeLog
egcs/gcc/config/mips/mips.md
md5sum: 2b40042e0bee9d74 6ddf3cf305fc8b2a 321579
--- /sloth/disk0/co/egcs-mainline/egcs/gcc/config/mips/mips.md Sun Oct 10 13:02:30 1999
+++ egcs/gcc/config/mips/mips.md Sun Oct 10 17:02:08 1999
@@ -2395,8 +2395,8 @@ (define_expand "div_trap"
}")
(define_insn "div_trap_normal"
- [(trap_if (eq (match_operand 0 "register_operand" "d")
- (match_operand 1 "true_reg_or_0_operand" "dJ"))
+ [(trap_if (eq (match_operand 0 "register_operand" "d,d")
+ (match_operand 1 "true_reg_or_0_operand" "d,J"))
(match_operand 2 "immediate_operand" ""))]
"!TARGET_MIPS16"
"*
@@ -2411,20 +2411,20 @@ (define_insn "div_trap_normal"
if ((int) REG_DEP_ANTI == (int) REG_NOTE_KIND (link)
&& GET_CODE (XEXP (link, 0)) == INSN
&& GET_CODE (PATTERN (XEXP (link, 0))) == TRAP_IF
- && REGNO (operands[1]) == 0)
+ && which_alternative == 1)
have_dep_anti = 1;
if (! have_dep_anti)
{
if (GENERATE_BRANCHLIKELY)
{
- if (GET_CODE (operands[1]) == CONST_INT)
+ if (which_alternative == 1)
return \"%(beql\\t%0,$0,1f\\n\\tbreak\\t%2\\n%~1:%)\";
else
return \"%(beql\\t%0,%1,1f\\n\\tbreak\\t%2\\n%~1:%)\";
}
else
{
- if (GET_CODE (operands[1]) == CONST_INT)
+ if (which_alternative == 1)
return \"%(bne\\t%0,$0,1f\\n\\tnop\\n\\tbreak\\t%2\\n%~1:%)\";
else
return \"%(bne\\t%0,%1,1f\\n\\tnop\\n\\tbreak\\t%2\\n%~1:%)\";
@@ -2439,8 +2439,8 @@ (define_insn "div_trap_normal"
;; The mips16 bne insns is a macro which uses reg 24 as an intermediate.
(define_insn "div_trap_mips16"
- [(trap_if (eq (match_operand 0 "register_operand" "d")
- (match_operand 1 "true_reg_or_0_operand" "dJ"))
+ [(trap_if (eq (match_operand 0 "register_operand" "d,d")
+ (match_operand 1 "true_reg_or_0_operand" "d,J"))
(match_operand 2 "immediate_operand" ""))
(clobber (reg:SI 24))]
"TARGET_MIPS16"
@@ -2456,12 +2456,12 @@ (define_insn "div_trap_mips16"
if ((int) REG_DEP_ANTI == (int) REG_NOTE_KIND (link)
&& GET_CODE (XEXP (link, 0)) == INSN
&& GET_CODE (PATTERN (XEXP (link, 0))) == TRAP_IF
- && REGNO (operands[1]) == 0)
+ && which_alternative == 1)
have_dep_anti = 1;
if (! have_dep_anti)
{
/* No branch delay slots on mips16. */
- if (GET_CODE (operands[1]) == CONST_INT)
+ if (which_alternative == 1)
return \"%(bnez\\t%0,1f\\n\\tbreak\\t%2\\n%~1:%)\";
else
return \"%(bne\\t%0,%1,1f\\n\\tbreak\\t%2\\n%~1:%)\";
============================================================