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movdi/df/xf patch for new_ia32_branch
- To: egcs-patches at egcs dot cygnus dot com
- Subject: movdi/df/xf patch for new_ia32_branch
- From: Jan Hubicka <hubicka at atrey dot karlin dot mff dot cuni dot cz>
- Date: Thu, 15 Jul 1999 22:52:27 +0200
Hi
This patch extends ix86_split_movdi to handle DF and XF mode values too.
This simplifies the splitters and unifies the complex stuff so I believe
it will be easier to maitain.
It also adds peepholer translating lea back to add when possible. This
helps to scheduling and reduces code size. Also fixes constraints for
movdf pattern.
The function ix86_split_long_move comes from my older patch that was quite
well tested, so hope that despite the relative complexity of it, it will
not contains too many bugs.
Intel manual recommends to use integer instructions whenever possible for
replacement of fp operations (some operations can be better done in integer
- moves, compares, fabs, fchsgn). Is there any chance to implement it
to gcc? Whats about changing the constraints to preffer "r" in these?
Honza
Thu Jul 15 16:47:41 EDT 1999 Jan Hubicka <hubicka@freesoft.cz>
* i386.md (movdi splitters): Use ix86_split_long_double.
(pushxf splitter): Likewise.
(movdf splitters): Likewise.
(pushdf splitter): Likewise.
(movxf_1): New splitters.
(pushxf): New splitters.
(movdf_1): Fix constraints.
(movxf_1): Supports integer register/immediate/memory moves as well.
*** i386.md1 Thu Jul 15 16:44:25 1999
--- i386.md Wed Jul 14 23:37:11 1999
***************
*** 1698,1714 ****
(define_split
[(set (match_operand:DI 0 "push_operand" "")
(match_operand:DI 1 "general_operand" ""))]
! ""
! [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 3))
! (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 2))]
! "
! {
! split_di (operands+1, 1, operands+2, operands+3);
! /* Compensate for the fact that we're changing stack offsets in
! the middle of this operation. */
! if (reg_mentioned_p (stack_pointer_rtx, operands[2]))
! operands[2] = adj_offsettable_operand (operands[2], 4);
! }")
;; %%% This multiword shite has got to go.
(define_split
--- 1698,1706 ----
(define_split
[(set (match_operand:DI 0 "push_operand" "")
(match_operand:DI 1 "general_operand" ""))]
! "reload_completed"
! [(const_int 0)]
! "if (!ix86_split_long_move (operands)) abort(); DONE;")
;; %%% This multiword shite has got to go.
(define_split
***************
*** 1716,1734 ****
(match_operand:DI 1 "general_operand" ""))
(clobber (reg:CC 17))]
"reload_completed"
! [(parallel [(set (match_dup 2) (match_dup 4))
(clobber (reg:CC 17))])
! (parallel [(set (match_dup 3) (match_dup 5))
(clobber (reg:CC 17))])]
! "if (ix86_split_movdi (operands)) DONE;")
(define_split
[(set (match_operand:DI 0 "general_operand" "")
(match_operand:DI 1 "general_operand" ""))]
"reload_completed"
! [(set (match_dup 2) (match_dup 4))
! (set (match_dup 3) (match_dup 5))]
! "if (ix86_split_movdi (operands)) DONE;")
(define_expand "movsf"
[(set (match_operand:SF 0 "general_operand" "")
--- 1708,1726 ----
(match_operand:DI 1 "general_operand" ""))
(clobber (reg:CC 17))]
"reload_completed"
! [(parallel [(set (match_dup 2) (match_dup 5))
(clobber (reg:CC 17))])
! (parallel [(set (match_dup 3) (match_dup 6))
(clobber (reg:CC 17))])]
! "if (ix86_split_long_move (operands)) DONE;")
(define_split
[(set (match_operand:DI 0 "general_operand" "")
(match_operand:DI 1 "general_operand" ""))]
"reload_completed"
! [(set (match_dup 2) (match_dup 5))
! (set (match_dup 3) (match_dup 6))]
! "if (ix86_split_long_move (operands)) DONE;")
(define_expand "movsf"
[(set (match_operand:SF 0 "general_operand" "")
***************
*** 1773,1779 ****
(define_insn "*movsf_1"
[(set (match_operand:SF 0 "nonimmediate_operand" "=f,m,f,*r,m,*r")
! (match_operand:SF 1 "general_operand" "fm,f,G,*rm,*r,G"))]
""
"*
{
--- 1765,1771 ----
(define_insn "*movsf_1"
[(set (match_operand:SF 0 "nonimmediate_operand" "=f,m,f,*r,m,*r")
! (match_operand:SF 1 "general_operand" "fm,f,G,*rm,F*r,GF"))]
""
"*
{
***************
*** 1875,1894 ****
[(set (match_operand:DF 0 "push_operand" "")
(match_operand:DF 1 "general_operand" ""))]
"reload_completed"
! [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 1))
! (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))]
! "
! {
! split_di (operands+1, 1, operands+0, operands+1);
! /* Compensate for the fact that we're changing stack offsets in
! the middle of this operation. */
! if (reg_mentioned_p (stack_pointer_rtx, operands[0]))
! operands[0] = adj_offsettable_operand (operands[0], 4);
! }")
(define_insn "*movdf_1"
[(set (match_operand:DF 0 "nonimmediate_operand" "=f,m,f,*r,m,*r")
! (match_operand:DF 1 "general_operand" "fm,f,G,*rm,*r,G"))]
""
"*
{
--- 1867,1878 ----
[(set (match_operand:DF 0 "push_operand" "")
(match_operand:DF 1 "general_operand" ""))]
"reload_completed"
! [(const_int 0)]
! "if (!ix86_split_long_move (operands)) abort(); DONE;")
(define_insn "*movdf_1"
[(set (match_operand:DF 0 "nonimmediate_operand" "=f,m,f,*r,m,*r")
! (match_operand:DF 1 "general_operand" "fm,f,G,*rm,F*r,F"))]
""
"*
{
***************
*** 1930,1937 ****
[(set_attr "type" "fmov,fmov,fmov,multi,multi,multi")])
(define_split
! [(set (match_operand:DF 0 "nonimmediate_operand" "")
! (match_operand:DF 1 "general_operand" ""))]
"reload_completed
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
&& ! (FP_REG_P (operands[0]) ||
--- 1914,1921 ----
[(set_attr "type" "fmov,fmov,fmov,multi,multi,multi")])
(define_split
! [(set (match_operand:DF 0 "general_operand" "")
! (match_operand:DF 1 "general_operand" ""))]
"reload_completed
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
&& ! (FP_REG_P (operands[0]) ||
***************
*** 1940,1949 ****
&& ! (FP_REG_P (operands[1]) ||
(GET_CODE (operands[1]) == SUBREG
&& FP_REG_P (SUBREG_REG (operands[1]))))"
! [(set (match_dup 0) (match_dup 2))
! (set (match_dup 1) (match_dup 3))]
! "split_di (operands+1, 1, operands+2, operands+3);
! split_di (operands+0, 1, operands+0, operands+1);")
(define_insn "swapdf"
[(set (match_operand:DF 0 "register_operand" "+f")
--- 1924,1932 ----
&& ! (FP_REG_P (operands[1]) ||
(GET_CODE (operands[1]) == SUBREG
&& FP_REG_P (SUBREG_REG (operands[1]))))"
! [(set (match_dup 2) (match_dup 5))
! (set (match_dup 3) (match_dup 6))]
! "if (ix86_split_long_move (operands)) DONE;")
(define_insn "swapdf"
[(set (match_operand:DF 0 "register_operand" "+f")
***************
*** 1968,1974 ****
(define_insn "*pushxf"
[(set (match_operand:XF 0 "push_operand" "=<,<")
! (match_operand:XF 1 "general_operand" "f,oF"))]
"TARGET_PUSH_MEMORY || !memory_operand (operands[1], XFmode)"
"*
{
--- 1951,1957 ----
(define_insn "*pushxf"
[(set (match_operand:XF 0 "push_operand" "=<,<")
! (match_operand:XF 1 "general_operand" "f,oF*r"))]
"TARGET_PUSH_MEMORY || !memory_operand (operands[1], XFmode)"
"*
{
***************
*** 2001,2045 ****
(define_split
[(set (match_operand:XF 0 "push_operand" "")
! (match_operand:XF 1 "memory_operand" ""))]
! "reload_completed"
! [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 2))
! (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 1))
! (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))]
! "
! {
! operands[0] = change_address (operands[1], SImode, NULL_RTX);
! operands[1] = adj_offsettable_operand (operands[0], 4);
! operands[2] = adj_offsettable_operand (operands[0], 8);
! /* Compensate for the fact that we're changing stack offsets in
! the middle of this operation. */
! if (reg_mentioned_p (stack_pointer_rtx, operands[1]))
! operands[1] = adj_offsettable_operand (operands[1], 4);
! if (reg_mentioned_p (stack_pointer_rtx, operands[0]))
! operands[0] = adj_offsettable_operand (operands[0], 8);
! }")
!
! (define_split
! [(set (match_operand:XF 0 "push_operand" "")
! (match_operand:XF 1 "immediate_operand" ""))]
! "reload_completed"
! [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 2))
! (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 1))
! (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))]
! "
! {
! REAL_VALUE_TYPE r; long l[3];
!
! REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
! REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
! operands[0] = GEN_INT (l[0]);
! operands[1] = GEN_INT (l[1]);
! operands[2] = GEN_INT (l[2]);
! }")
(define_insn "*movxf_1"
! [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f")
! (match_operand:XF 1 "general_operand" "fm,f,G"))]
""
"*
{
--- 1984,1998 ----
(define_split
[(set (match_operand:XF 0 "push_operand" "")
! (match_operand:XF 1 "general_operand" ""))]
! "reload_completed
! && (!REG_P (operands[1]) || !FP_REGNO_P (REGNO (operands[1])))"
! [(const_int 0)]
! "if (!ix86_split_long_move (operands)) abort(); DONE;")
(define_insn "*movxf_1"
! [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,*r,m,*r")
! (match_operand:XF 1 "general_operand" "fm,f,G,*rm,F*r,F"))]
""
"*
{
***************
*** 2070,2079 ****
return \"fld1\";
}
break;
}
abort();
}"
! [(set_attr "type" "fmov")])
(define_insn "swapxf"
[(set (match_operand:XF 0 "register_operand" "+f")
--- 2023,2052 ----
return \"fld1\";
}
break;
+ case 3:
+ case 4:
+ case 5:
+ return \"#\";
}
abort();
}"
! [(set_attr "type" "fmov,fmov,fmov,multi,multi,multi")])
!
! (define_split
! [(set (match_operand:XF 0 "general_operand" "")
! (match_operand:XF 1 "general_operand" ""))]
! "reload_completed
! && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
! && ! (FP_REG_P (operands[0]) ||
! (GET_CODE (operands[0]) == SUBREG
! && FP_REG_P (SUBREG_REG (operands[0]))))
! && ! (FP_REG_P (operands[1]) ||
! (GET_CODE (operands[1]) == SUBREG
! && FP_REG_P (SUBREG_REG (operands[1]))))"
! [(set (match_dup 2) (match_dup 5))
! (set (match_dup 3) (match_dup 6))
! (set (match_dup 4) (match_dup 7))]
! "if (ix86_split_long_move (operands)) DONE;")
(define_insn "swapxf"
[(set (match_operand:XF 0 "register_operand" "+f")
***************
*** 3058,3063 ****
--- 3031,3049 ----
return \"lea{l}\\t{%a1, %0|%0, %a1}\";
}"
[(set_attr "type" "lea")])
+
+ ;; Add is two byte shorter and usually have better scheduling properties.
+ ;; This insn can be result of splitters for push?f.
+ (define_peephole2
+ [(set (match_operand:SI 0 "register_operand" "")
+ (plus:SI (match_dup 0)
+ (match_operand:SI 1 "nonmemory_operand" "")))]
+ "reg_dead_p (insn, gen_rtx_REG (CCmode, FLAGS_REG))
+ && (optimize_size || !TARGET_PENTIUMPRO)"
+ [(parallel [(set (match_dup 0)
+ (plus:SI (match_dup 0)
+ (match_dup 1)))
+ (clobber (reg:CC 17))])])
(define_insn "*addsi_1"
[(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm,r")
*** i386.c1 Wed Jul 14 11:17:32 1999
--- i386.c Thu Jul 15 16:43:23 1999
*************** ix86_expand_fp_movcc (operands)
*** 4584,4617 ****
return 1;
}
int
! ix86_split_movdi (operands)
! rtx operands[];
{
! split_di (operands+0, 1, operands+2, operands+3);
! split_di (operands+1, 1, operands+4, operands+5);
! if (reg_overlap_mentioned_p (operands[2], operands[1]))
{
! rtx tmp;
! if (!reg_overlap_mentioned_p (operands[3], operands[4]))
{
! tmp = operands[2], operands[2] = operands[3], operands[3] = tmp;
! tmp = operands[4], operands[4] = operands[5], operands[5] = tmp;
}
else
{
! emit_insn (gen_push (operands[4]));
! emit_insn (gen_rtx_SET (VOIDmode, operands[3], operands[5]));
! emit_insn (gen_popsi1 (operands[2]));
! return 1; /* DONE */
}
}
return 0;
}
!
void
ix86_split_ashldi (operands, scratch)
rtx *operands, scratch;
--- 4584,4803 ----
return 1;
}
+
+ /* split operand to SI mode parts. Similar to split_di, but works for
+ floating point parameters and nonoffsetable references too.
+
+ For autodecrementing it returns just pointers to first part and
+ expect, that values will be saved in right order.
+ Maximally three parts are generated. */
+
+ static void
+ ix86_split_to_parts (operand, parts, mode)
+ rtx operand, *parts;
+ enum machine_mode mode;
+ {
+ int size;
+ size = GET_MODE_SIZE (mode) / 4;
+
+ if (size < 2 || size > 3)
+ abort ();
+
+ if (GET_CODE (operand) == MEM && !offsettable_memref_p (operand))
+ {
+ /* Only non-offsetable references we handle are pushes. */
+ if (GET_CODE (XEXP (operand, 0)) != PRE_DEC) abort();
+ PUT_MODE (operand, SImode);
+ parts[0] = parts[1] = parts[2] = operand;
+ }
+ else
+ {
+ if (mode == DImode)
+ split_di (&operand, 1, &parts[0], &parts[1]);
+ else
+ {
+ if (REG_P (operand))
+ {
+ if (!reload_completed)
+ abort();
+ parts[0] = gen_rtx_REG (SImode, REGNO (operand) + 0);
+ parts[1] = gen_rtx_REG (SImode, REGNO (operand) + 1);
+ if (size == 3)
+ parts[2] = gen_rtx_REG (SImode, REGNO (operand) + 2);
+ }
+ else if (offsettable_memref_p (operand))
+ {
+ PUT_MODE (operand, SImode);
+ parts[0] = operand;
+ parts[1] = adj_offsettable_operand (operand, 4);
+ parts[2] = adj_offsettable_operand (operand, 8);
+ }
+ else if (GET_CODE (operand) == CONST_DOUBLE)
+ {
+ REAL_VALUE_TYPE r;
+ long l[3];
+
+ REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
+ switch (mode)
+ {
+ case XFmode:
+ REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
+ parts[2] = GEN_INT (l[2]);
+ break;
+ case DFmode:
+ REAL_VALUE_TO_TARGET_DOUBLE (r, l);
+ break;
+ default:
+ abort ();
+ }
+ parts[0] = GEN_INT (l[0]);
+ parts[1] = GEN_INT (l[1]);
+ }
+ else
+ abort ();
+ }
+ }
+ return size;
+ }
+
+ /* Emit insns to perform move or push of DI, DF and XF values.
+ Return 0 in case normal moves are needed. And then takes care to
+ output them. Operands 2-4 contains input values in right order and
+ operands 5-7 output values. This technique is usefull to preserve possible
+ clobbers of flags.
+
+ For push operands 0 is returned and necesary instructions are emited. */
int
! ix86_split_long_move (operands1)
! rtx *operands1;
{
! rtx part[2][3];
! rtx operands[2];
! int size = GET_MODE_SIZE (GET_MODE (operands1[0])) / 4;
! int push = 0;
! int colisions = 0;
!
!
! /* Make our own copy to avoid clobbering of the operands. */
! operands[0] = copy_rtx (operands1[0]);
! operands[1] = copy_rtx (operands1[1]);
!
! if (size < 2 || size > 3)
! abort ();
!
! /* Only non-offsetable memory reference we handle is push. */
! if (GET_CODE (operands[0]) == MEM && !offsettable_memref_p (operands[0]))
{
! if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
{
! if (REGNO (XEXP (XEXP (operands[0], 0), 0)) != STACK_POINTER_REGNUM)
! abort ();
! push = 1;
}
else
+ abort ();
+ }
+
+ ix86_split_to_parts (operands[0], part[0], GET_MODE (operands1[0]));
+ ix86_split_to_parts (operands[1], part[1], GET_MODE (operands1[0]));
+
+ /* When emiting push, takce care for source operands from stack. */
+ if (push && GET_CODE (operands[1]) == MEM)
+ {
+ if (reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
{
! if (size == 3)
! part[1][1] = part[1][2];
! part[1][0] = part[1][1];
! }
! }
!
! /* We need to do copy in right order in case address register of source
! conflict with destination. */
!
! if (REG_P (part[0][0]) && GET_CODE (part[1][0]) == MEM)
! {
! colisions =
! (reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0)) != 0) +
! (reg_overlap_mentioned_p (part[0][1], XEXP (part[1][0], 0)) != 0) +
! (size == 3
! && reg_overlap_mentioned_p (part[0][2], XEXP (part[1][0], 0)) != 0);
! /* Collision in the middle part can be handled by reordering. */
! if (colisions == 1 && size == 3
! && reg_overlap_mentioned_p (part[0][1], XEXP (part[1][0], 0)))
! {
! rtx tmp;
! tmp = part[0][1];
! part[0][1] = part[0][2];
! part[0][2] = tmp;
! tmp = part[1][1];
! part[1][1] = part[1][2];
! part[1][2] = tmp;
! }
! else
! /* If there are more colisions, we can't handle it by reorder.
! Do lea to last part and use 1 coliding mode. */
! if (colisions > 1
! || (size == 3
! && reg_overlap_mentioned_p (part[0][1], XEXP (part[1][0], 0))))
! {
! colisions = 1;
! emit_insn (gen_rtx_SET (SImode, part[0][size - 1],
! XEXP (part[1][0], 0)));
! part[1][0] = gen_rtx_MEM (SImode, part[0][size - 1]);
! part[1][1] = adj_offsettable_operand (part[1][0], 4);
! part[1][2] = adj_offsettable_operand (part[1][0], 8);
}
}
+ /* Push needs to be handled separately. */
+ if (push)
+ {
+ if (size == 3)
+ emit_insn (gen_push (part[1][2]));
+ debug_rtx (emit_insn (gen_push (part[1][1])));
+ debug_rtx (emit_insn (gen_push (part[1][0])));
+ return 1;
+ }
+
+ /* Choose correct order to not overwrite the source before it is copied. */
+ if ((REG_P (part[0][0]) && REG_P (part[1][1])
+ && (REGNO (part[0][0]) == REGNO (part[1][1])
+ || (size == 3 && REGNO (part[0][0]) == REGNO (part[1][2]))))
+ || (colisions
+ && reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0))))
+ {
+ if (size == 3)
+ {
+ operands1[2] = part[0][2];
+ operands1[3] = part[0][1];
+ operands1[4] = part[0][0];
+ operands1[5] = part[1][2];
+ operands1[6] = part[1][1];
+ operands1[7] = part[1][0];
+ }
+ else
+ {
+ operands1[2] = part[0][1];
+ operands1[3] = part[0][0];
+ operands1[5] = part[1][1];
+ operands1[6] = part[1][0];
+ }
+ }
+ else
+ {
+ operands1[2] = part[0][0];
+ operands1[3] = part[0][1];
+ operands1[4] = part[0][2];
+ operands1[5] = part[1][0];
+ operands1[6] = part[1][1];
+ operands1[7] = part[1][2];
+ }
return 0;
}
!
void
ix86_split_ashldi (operands, scratch)
rtx *operands, scratch;
*** i386.h1 Wed Jul 14 11:19:24 1999
--- i386.h Wed Jul 14 23:46:05 1999
*************** extern void ix86_expand_branch XPARAMS((
*** 2488,2494 ****
extern int ix86_expand_setcc XPARAMS((xcode, int, xrtx));
extern int ix86_expand_int_movcc XPARAMS((xrtx[]));
extern int ix86_expand_fp_movcc XPARAMS((xrtx[]));
! extern int ix86_split_movdi XPARAMS((xrtx[]));
extern void ix86_split_ashldi XPARAMS((xrtx *, xrtx));
extern void ix86_split_ashrdi XPARAMS((xrtx *, xrtx));
extern void ix86_split_lshrdi XPARAMS((xrtx *, xrtx));
--- 2488,2494 ----
extern int ix86_expand_setcc XPARAMS((xcode, int, xrtx));
extern int ix86_expand_int_movcc XPARAMS((xrtx[]));
extern int ix86_expand_fp_movcc XPARAMS((xrtx[]));
! extern int ix86_split_long_move XPARAMS((xrtx[]));
extern void ix86_split_ashldi XPARAMS((xrtx *, xrtx));
extern void ix86_split_ashrdi XPARAMS((xrtx *, xrtx));
extern void ix86_split_lshrdi XPARAMS((xrtx *, xrtx));