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PA64 infrastructure work
- To: gcc-patches@gcc.gnu.org
- Subject: PA64 infrastructure work
- From: Jeffrey A Law <law@cygnus.com>
- Date: Tue, 27 Jul 1999 23:19:26 -0600
- Reply-To: law@cygnus.com
This is a minor infrastructure change to make it easier to work on 64bit
code generation for the PA.
Basically the prologue/epilogue code wants to be able to generate stores
with post increment and loads with pre decrement. The way we currently do
that is to call a generator function for a 32bit specific pattern.
This patch creates two generic expanders (one for each desired operation) which
gives me a hook I can later use to switch between 32bit and 64bit code
generation strategies. It also does some slight pattern renaming.
* pa.md (post_store, pre_load): New expanders.
(post_stwm, pre_ldwm): Renamed to post_stw and pre_ldw respectively.
(post_ldwm, pre_stwm): Make these unnamed patterns since we never
need to directly generate RTL for them.
* pa.c (hppa_expand_prologue, hppa_expand_epilogue): Corresponding
changes.
Index: pa.c
===================================================================
RCS file: /egcs/carton/cvsfiles/egcs/gcc/config/pa/pa.c,v
retrieving revision 1.43
diff -c -3 -p -r1.43 pa.c
*** pa.c 1999/07/26 01:21:57 1.43
--- pa.c 1999/07/28 05:14:57
*************** hppa_expand_prologue()
*** 2688,2694 ****
emit_move_insn (tmpreg, frame_pointer_rtx);
emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
if (VAL_14_BITS_P (actual_fsize))
! emit_insn (gen_post_stwm (stack_pointer_rtx, tmpreg, size_rtx));
else
{
/* It is incorrect to store the saved frame pointer at *sp,
--- 2688,2694 ----
emit_move_insn (tmpreg, frame_pointer_rtx);
emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
if (VAL_14_BITS_P (actual_fsize))
! emit_insn (gen_post_store (stack_pointer_rtx, tmpreg, size_rtx));
else
{
/* It is incorrect to store the saved frame pointer at *sp,
*************** hppa_expand_prologue()
*** 2697,2703 ****
So instead use stwm to store at *sp and post-increment the
stack pointer as an atomic operation. Then increment sp to
finish allocating the new frame. */
! emit_insn (gen_post_stwm (stack_pointer_rtx, tmpreg, GEN_INT (64)));
set_reg_plus_d (STACK_POINTER_REGNUM,
STACK_POINTER_REGNUM,
actual_fsize - 64);
--- 2697,2704 ----
So instead use stwm to store at *sp and post-increment the
stack pointer as an atomic operation. Then increment sp to
finish allocating the new frame. */
! emit_insn (gen_post_store (stack_pointer_rtx, tmpreg,
! GEN_INT (64)));
set_reg_plus_d (STACK_POINTER_REGNUM,
STACK_POINTER_REGNUM,
actual_fsize - 64);
*************** hppa_expand_prologue()
*** 2820,2828 ****
if (merge_sp_adjust_with_store)
{
merge_sp_adjust_with_store = 0;
! emit_insn (gen_post_stwm (stack_pointer_rtx,
! gen_rtx_REG (word_mode, i),
! GEN_INT (-offset)));
}
else
store_reg (i, offset, STACK_POINTER_REGNUM);
--- 2821,2829 ----
if (merge_sp_adjust_with_store)
{
merge_sp_adjust_with_store = 0;
! emit_insn (gen_post_store (stack_pointer_rtx,
! gen_rtx_REG (word_mode, i),
! GEN_INT (-offset)));
}
else
store_reg (i, offset, STACK_POINTER_REGNUM);
*************** hppa_expand_epilogue ()
*** 3032,3044 ****
else if (frame_pointer_needed)
{
set_reg_plus_d (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, 64);
! emit_insn (gen_pre_ldwm (frame_pointer_rtx,
stack_pointer_rtx,
GEN_INT (-64)));
}
/* If we were deferring a callee register restore, do it now. */
else if (! frame_pointer_needed && merge_sp_adjust_with_load)
! emit_insn (gen_pre_ldwm (gen_rtx_REG (word_mode,
merge_sp_adjust_with_load),
stack_pointer_rtx,
GEN_INT (- actual_fsize)));
else if (actual_fsize != 0)
--- 3033,3045 ----
else if (frame_pointer_needed)
{
set_reg_plus_d (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, 64);
! emit_insn (gen_pre_load (frame_pointer_rtx,
stack_pointer_rtx,
GEN_INT (-64)));
}
/* If we were deferring a callee register restore, do it now. */
else if (! frame_pointer_needed && merge_sp_adjust_with_load)
! emit_insn (gen_pre_load (gen_rtx_REG (word_mode,
merge_sp_adjust_with_load),
stack_pointer_rtx,
GEN_INT (- actual_fsize)));
else if (actual_fsize != 0)
Index: pa.md
===================================================================
RCS file: /egcs/carton/cvsfiles/egcs/gcc/config/pa/pa.md,v
retrieving revision 1.34
diff -c -3 -p -r1.34 pa.md
*** pa.md 1999/06/07 19:36:20 1.34
--- pa.md 1999/07/28 05:15:01
***************
*** 1478,1484 ****
;; Load or store with base-register modification.
! (define_insn "pre_ldwm"
[(set (match_operand:SI 0 "register_operand" "=r")
(mem:SI (plus:SI (match_operand:SI 1 "register_operand" "+r")
(match_operand:SI 2 "pre_cint_operand" ""))))
--- 1478,1497 ----
;; Load or store with base-register modification.
! (define_expand "pre_load"
! [(parallel [(set (match_operand:SI 0 "register_operand" "")
! (mem (plus (match_operand 1 "register_operand" "")
! (match_operand 2 "pre_cint_operand" ""))))
! (set (match_dup 1)
! (plus (match_dup 1) (match_dup 2)))])]
! ""
! "
! {
! emit_insn (gen_pre_ldw (operands[0], operands[1], operands[2]));
! DONE;
! }")
!
! (define_insn "pre_ldw"
[(set (match_operand:SI 0 "register_operand" "=r")
(mem:SI (plus:SI (match_operand:SI 1 "register_operand" "+r")
(match_operand:SI 2 "pre_cint_operand" ""))))
***************
*** 1494,1500 ****
[(set_attr "type" "load")
(set_attr "length" "4")])
! (define_insn "pre_stwm"
[(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "+r")
(match_operand:SI 1 "pre_cint_operand" "")))
(match_operand:SI 2 "reg_or_0_operand" "rM"))
--- 1507,1513 ----
[(set_attr "type" "load")
(set_attr "length" "4")])
! (define_insn ""
[(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "+r")
(match_operand:SI 1 "pre_cint_operand" "")))
(match_operand:SI 2 "reg_or_0_operand" "rM"))
***************
*** 1510,1516 ****
[(set_attr "type" "store")
(set_attr "length" "4")])
! (define_insn "post_ldwm"
[(set (match_operand:SI 0 "register_operand" "=r")
(mem:SI (match_operand:SI 1 "register_operand" "+r")))
(set (match_dup 1)
--- 1523,1529 ----
[(set_attr "type" "store")
(set_attr "length" "4")])
! (define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r")
(mem:SI (match_operand:SI 1 "register_operand" "+r")))
(set (match_dup 1)
***************
*** 1525,1532 ****
}"
[(set_attr "type" "load")
(set_attr "length" "4")])
! (define_insn "post_stwm"
[(set (mem:SI (match_operand:SI 0 "register_operand" "+r"))
(match_operand:SI 1 "reg_or_0_operand" "rM"))
(set (match_dup 0)
--- 1538,1558 ----
}"
[(set_attr "type" "load")
(set_attr "length" "4")])
+
+ (define_expand "post_store"
+ [(parallel [(set (mem (match_operand 0 "register_operand" ""))
+ (match_operand 1 "reg_or_0_operand" ""))
+ (set (match_dup 0)
+ (plus (match_dup 0)
+ (match_operand 2 "post_cint_operand" "")))])]
+ ""
+ "
+ {
+ emit_insn (gen_post_stw (operands[0], operands[1], operands[2]));
+ DONE;
+ }")
! (define_insn "post_stw"
[(set (mem:SI (match_operand:SI 0 "register_operand" "+r"))
(match_operand:SI 1 "reg_or_0_operand" "rM"))
(set (match_dup 0)