This is the mail archive of the
gcc-patches@gcc.gnu.org
mailing list for the GCC project.
mips.md bugfix
- To: egcs-patches at egcs dot cygnus dot com
- Subject: mips.md bugfix
- From: Jeffrey A Law <law at cygnus dot com>
- Date: Tue, 29 Jun 1999 03:02:16 -0600
- Reply-To: law at cygnus dot com
This fixes the infamous out of range addresses on certain mips platforms using
an idea Jim had a while back.
Basically Jim & I agreed that the bug was in the backend (not the front-end
like some folks had argued). We differed on precisely what code in the backend
was actually wrong (GO_IF_LEGITIMATE_ADDRESS vs lea patterns).
I've gone with Jim's suggestion and created load address patterns. Note
they're at the end of the MD file and will only be matched when none of
the normal movxx/addxx patterns match the rtl we generate for some address
computations.
A similar patch was checked into the gcc-2.95 branch (length computations
are different between the branch & mainline sources).
* mips.md (leasi, leadi): New patterns.
Index: mips.md
===================================================================
RCS file: /egcs/carton/cvsfiles/egcs/gcc/config/mips/mips.md,v
retrieving revision 1.55
diff -c -3 -p -r1.55 mips.md
*** mips.md 1999/03/02 07:07:33 1.55
--- mips.md 1999/06/29 08:53:03
*************** move\\t%0,%z4\\n\\
*** 10416,10418 ****
--- 10416,10442 ----
[(set_attr "type" "branch")
(set_attr "mode" "none")
(set_attr "length" "8")])
+
+ ;; For the rare case where we need to load an address into a register
+ ;; that can not be recognized by the normal movsi/addsi instructions.
+ ;; I have no idea how many insns this can actually generate. It should
+ ;; be rare, so over-estimating as 10 instructions should not have any
+ ;; real performance impact.
+ (define_insn "leasi"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (match_operand:SI 1 "address_operand" "p"))]
+ "Pmode == SImode"
+ "la %0,%a1"
+ [(set_attr "type" "arith")
+ (set_attr "mode" "SI")
+ (set_attr "length" "40")])
+
+ ;; Similarly for targets where we have 64bit pointers.
+ (define_insn "leadi"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (match_operand:DI 1 "address_operand" "p"))]
+ "Pmode == DImode"
+ "la %0,%a1"
+ [(set_attr "type" "arith")
+ (set_attr "mode" "DI")
+ (set_attr "length" "40")])