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MIPS PATCH: -mips2 -mlong64
- To: egcs-patches at egcs dot cygnus dot com
- Subject: MIPS PATCH: -mips2 -mlong64
- From: Gavin Romig-Koch <gavin at cygnus dot com>
- Date: Fri, 5 Mar 1999 18:24:41 -0500 (EST)
The point of this patch is to allow the user to have 64-bit longs on
a 32-bit machines by separating the size of pointers from the -mlong64
flag. With this patch pointer widths are the smaller of the width of
longs or the width of the gp registers.
If no one sees a problem with this, or otherwise objects, I'll commit
it in a few days.
-gavin...
* config/mips/iris.h (CTORS_SECTION_ASM_OP,DTORS_SECTION_ASM_OP,
dtors_section): Use Pmode == DImode rather than TARGET_LONG64.
* config/mips/mips.c (override_options): Allow -mlong64 and
-mint64 with -mips2 or less.
* config/mips/mips.h (MASK_LONG64): Fix comment.
(POINTER_SIZE): Use Pmode == DImode rather than TARGET_LONG64.
(Pmode): Make Pmode the smaller of longs or gp registers.
* invoke.texi: Note the new size for pointers.
Index: gcc/config/mips/iris6.h
===================================================================
RCS file: /egcs/carton/cvsfiles/egcs/gcc/config/mips/iris6.h,v
retrieving revision 1.14
diff -c -p -r1.14 iris6.h
*** gcc/config/mips/iris6.h 1998/12/16 21:09:10 1.14
--- gcc/config/mips/iris6.h 1999/03/05 23:05:44
*************** Boston, MA 02111-1307, USA. */
*** 263,271 ****
/* If we are included from varasm.c, these need to depend on -mabi. */
#define CTORS_SECTION_ASM_OP \
! (TARGET_LONG64 ? ".section\t.ctors,1,2,0,8" : ".section\t.ctors,1,2,0,4")
#define DTORS_SECTION_ASM_OP \
! (TARGET_LONG64 ? ".section\t.dtors,1,2,0,8" : ".section\t.dtors,1,2,0,4")
#endif /* defined (CRT_BEGIN) || defined (CRT_END) */
/* dwarf2out will handle padding this data properly. We definitely don't
--- 263,271 ----
/* If we are included from varasm.c, these need to depend on -mabi. */
#define CTORS_SECTION_ASM_OP \
! (Pmode == DImode ? ".section\t.ctors,1,2,0,8" : ".section\t.ctors,1,2,0,4")
#define DTORS_SECTION_ASM_OP \
! (Pmode == DImode ? ".section\t.dtors,1,2,0,8" : ".section\t.dtors,1,2,0,4")
#endif /* defined (CRT_BEGIN) || defined (CRT_END) */
/* dwarf2out will handle padding this data properly. We definitely don't
*************** dtors_section () \
*** 341,347 ****
do { \
ctors_section (); \
fprintf (FILE, "\t%s\t ", \
! TARGET_LONG64 ? ".dword" : ".word"); \
assemble_name (FILE, NAME); \
fprintf (FILE, "\n"); \
} while (0)
--- 341,347 ----
do { \
ctors_section (); \
fprintf (FILE, "\t%s\t ", \
! (Pmode == DImode) ? ".dword" : ".word"); \
assemble_name (FILE, NAME); \
fprintf (FILE, "\n"); \
} while (0)
*************** dtors_section () \
*** 352,358 ****
do { \
dtors_section (); \
fprintf (FILE, "\t%s\t ", \
! TARGET_LONG64 ? ".dword" : ".word"); \
assemble_name (FILE, NAME); \
fprintf (FILE, "\n"); \
} while (0)
--- 352,358 ----
do { \
dtors_section (); \
fprintf (FILE, "\t%s\t ", \
! (Pmode == DImode) ? ".dword" : ".word"); \
assemble_name (FILE, NAME); \
fprintf (FILE, "\n"); \
} while (0)
Index: gcc/config/mips/mips.c
===================================================================
RCS file: /egcs/carton/cvsfiles/egcs/gcc/config/mips/mips.c,v
retrieving revision 1.51
diff -c -p -r1.51 mips.c
*** gcc/config/mips/mips.c 1999/02/22 19:38:39 1.51
--- gcc/config/mips/mips.c 1999/03/05 23:05:52
*************** override_options ()
*** 4272,4284 ****
/* make sure sizes of ints/longs/etc. are ok */
if (mips_isa < 3)
{
! if (TARGET_INT64)
! fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit ints");
!
! else if (TARGET_LONG64)
! fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit longs");
!
! else if (TARGET_FLOAT64)
fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit fp registers");
else if (TARGET_64BIT)
--- 4272,4278 ----
/* make sure sizes of ints/longs/etc. are ok */
if (mips_isa < 3)
{
! if (TARGET_FLOAT64)
fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit fp registers");
else if (TARGET_64BIT)
Index: gcc/config/mips/mips.h
===================================================================
RCS file: /egcs/carton/cvsfiles/egcs/gcc/config/mips/mips.h,v
retrieving revision 1.45
diff -c -p -r1.45 mips.h
*** gcc/config/mips/mips.h 1999/02/03 13:04:20 1.45
--- gcc/config/mips/mips.h 1999/03/05 23:06:00
*************** extern void mips_select_section ();
*** 316,322 ****
/* Bits for real switches */
#define MASK_INT64 0x00000001 /* ints are 64 bits */
! #define MASK_LONG64 0x00000002 /* longs and pointers are 64 bits */
#define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
#define MASK_GPOPT 0x00000008 /* Optimize for global pointer */
#define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
--- 316,322 ----
/* Bits for real switches */
#define MASK_INT64 0x00000001 /* ints are 64 bits */
! #define MASK_LONG64 0x00000002 /* longs are 64 bits */
#define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
#define MASK_GPOPT 0x00000008 /* Optimize for global pointer */
#define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
*************** do { \
*** 1345,1351 ****
/* Width in bits of a pointer.
See also the macro `Pmode' defined below. */
#ifndef POINTER_SIZE
! #define POINTER_SIZE (TARGET_LONG64 ? 64 : 32)
#endif
/* Allocation boundary (in *bits*) for storing pointers in memory. */
--- 1345,1351 ----
/* Width in bits of a pointer.
See also the macro `Pmode' defined below. */
#ifndef POINTER_SIZE
! #define POINTER_SIZE (Pmode == DImode ? 64 : 32)
#endif
/* Allocation boundary (in *bits*) for storing pointers in memory. */
*************** while (0)
*** 3241,3250 ****
/* Specify the machine mode that pointers have.
After generation of rtl, the compiler makes no further distinction
! between pointers and any other objects of this machine mode. */
#ifndef Pmode
! #define Pmode ((enum machine_mode)(TARGET_LONG64 ? DImode : SImode))
#endif
/* A function address in a call instruction
--- 3241,3252 ----
/* Specify the machine mode that pointers have.
After generation of rtl, the compiler makes no further distinction
! between pointers and any other objects of this machine mode.
+ For MIPS we make pointers are the smaller of longs and gp-registers. */
+
#ifndef Pmode
! #define Pmode ((enum machine_mode)((TARGET_LONG64 && TARGET_64BIT) ? DImode : SImode))
#endif
/* A function address in a call instruction
Index: gcc/invoke.texi
===================================================================
RCS file: /egcs/carton/cvsfiles/egcs/gcc/invoke.texi,v
retrieving revision 1.94
diff -c -p -r1.94 invoke.texi
*** gcc/invoke.texi 1999/02/22 16:47:47 1.94
--- gcc/invoke.texi 1999/03/05 23:06:07
*************** ISA level.
*** 4766,4772 ****
@item -mips3
Issue instructions from level 3 of the MIPS ISA (64 bit instructions).
@samp{r4000} is the default @var{cpu type} at this ISA level.
- This option does not change the sizes of any of the C data types.
@item -mips4
Issue instructions from level 4 of the MIPS ISA. @samp{r8000} is the
--- 4766,4771 ----
*************** Assume that 32 64-bit general purpose re
*** 4789,4800 ****
the default when the @samp{-mips3} option is used.
@item -mint64
! Types long, int, and pointer are 64 bits. This works only if @samp{-mips3}
! is also specified.
@item -mlong64
! Types long and pointer are 64 bits, and type int is 32 bits.
! This works only if @samp{-mips3} is also specified.
@itemx -mabi=32
@itemx -mabi=n32
--- 4788,4801 ----
the default when the @samp{-mips3} option is used.
@item -mint64
! For int and long types to be 64 bits wide. See @samp{-mlong64} for an
! explanation of the width of pointers.
@item -mlong64
! Force long types to be 64 bits wide.
!
! The width of pointer types is the smaller of the width of longs
! or the width of general purpose registers.
@itemx -mabi=32
@itemx -mabi=n32