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Re: ppc patch
- To: law at cygnus dot com
- Subject: Re: ppc patch
- From: David Edelsohn <dje at watson dot ibm dot com>
- Date: Sat, 22 Aug 1998 23:05:30 -0400
- Cc: meissner at cygnus dot com, egcs-patches at cygnus dot com
The movdf patterns use %L print_operand case for the
register/memory pair. This case *cannot* handle indexed addressing. I
think the 'o' was trying to prevent indexed addressing when a memory pair
The problem is that by the time the compiler gets to the output
template, adding a constant increment to reference the neighboring memory
location is easy as long as the original reference included an offset that
was zero or constant. If the offset was a register, i.e. an indexed
address, we cannot add another increment without inserting an additional
There seem to be other patterns using 'm' with %L which have been
added since Kenner's original rs6000 port and haven't failed, but programs
which would produce indexed DImode (on a 32-bit target) and TImode
variables probably are more rare. GCC knows how to generate indexed
addresses for PowerPC but it is not very effective at it.
Is there any way to prevent indexed addressing when
HARD_REGNO_NREGS is greater than 1 for the hard registers allocated?
I.e., indexing is not okay when DFmode is assigned to two 32-bit GPRs, but
is fine with FPRs. The PRE_INC / PRE_DEC is fine, but indexing is not.
We have to allow DFmode in GPRs, not just for soft-float.