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PATCH for invoke.texi MIPS switches
- To: Jeff Law <law at cygnus dot com>, Jim Wilson <wilson at cygnus dot com>
- Subject: PATCH for invoke.texi MIPS switches
- From: Mark Mitchell <mark at markmitchell dot com>
- Date: Mon, 8 Jun 1998 14:40:16 -0700
- Cc: egcs-patches at cygnus dot com
- Reply-to: mark at markmitchell dot com
Here's some documentation for a couple of MIPS switches that seem not
to be documented at present. It's not *great* documentation, but it's
probably better than nothing at all.
OK to check in?
--
Mark Mitchell mark@markmitchell.com
Mark Mitchell Consulting http://www.markmitchell.com
Mon Jun 8 14:38:12 1998 Mark Mitchell <mark@markmitchell.com>
* invoke.texi: Add documentation for -mips4 and -mabi=*.
Index: invoke.texi
===================================================================
RCS file: /egcs/carton/cvsfiles/egcs/gcc/invoke.texi,v
retrieving revision 1.44
diff -c -p -r1.44 invoke.texi
*** invoke.texi 1998/06/05 15:13:49 1.44
--- invoke.texi 1998/06/08 21:35:20
*************** in the following sections.
*** 315,321 ****
-mabicalls -mcpu=@var{cpu type} -membedded-data
-membedded-pic -mfp32 -mfp64 -mgas -mgp32 -mgp64
-mgpopt -mhalf-pic -mhard-float -mint64 -mips1
! -mips2 -mips3 -mlong64 -mlong-calls -mmemcpy
-mmips-as -mmips-tfile -mno-abicalls
-mno-embedded-data -mno-embedded-pic
-mno-gpopt -mno-long-calls
--- 315,321 ----
-mabicalls -mcpu=@var{cpu type} -membedded-data
-membedded-pic -mfp32 -mfp64 -mgas -mgp32 -mgp64
-mgpopt -mhalf-pic -mhard-float -mint64 -mips1
! -mips2 -mips3 -mips4 -mlong64 -mlong-calls -mmemcpy
-mmips-as -mmips-tfile -mno-abicalls
-mno-embedded-data -mno-embedded-pic
-mno-gpopt -mno-long-calls
*************** in the following sections.
*** 323,328 ****
--- 323,330 ----
-mrnames -msoft-float
-m4650 -msingle-float -mmad
-mstats -EL -EB -G @var{num} -nocpp
+ -mabi=o32 -mabi=32 -mabi=n32 -mabi=n64 -mabi=64
+ -mabi=eabi
@emph{i386 Options}
-mcpu=@var{cpu type}
*************** Issue instructions from level 3 of the M
*** 4615,4620 ****
--- 4617,4626 ----
@samp{r4000} is the default @var{cpu type} at this ISA level.
This option does not change the sizes of any of the C data types.
+ @item -mips4
+ Issue instructions from level 4 of the MIPS ISA. @samp{r8000} is the
+ default @var{cpu type} at this ISA level.
+
@item -mfp32
Assume that 32 32-bit floating point registers are available. This is
the default.
*************** is also specified.
*** 4639,4644 ****
--- 4645,4658 ----
Types long and pointer are 64 bits, and type int is 32 bits.
This works only if @samp{-mips3} is also specified.
+ @item -mabi=o32
+ @itemx -mabi=32
+ @itemx -mabi=n32
+ @itemx -mabi=n64
+ @itemx -mabi=64
+ @itemx -mabi=eabi
+ Generate code for the indicated ABI.
+
@item -mmips-as
Generate code for the MIPS assembler, and invoke @file{mips-tfile} to
add normal debug information. This is the default for all