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Re: Memory model release/acquire mode interactions of relaxed atomic operations
On 05/05/17 18:26, Toebs Douglass wrote:
> I may be wrong, but I think you might be thinking about store barriers
> being built into atomic operations; if so, I don't mean that in what I
> say. I mean that a bare atomic operation (LL/SC / LOCK), bereft of
> memory barriers, forces a store to memory, and that this in turn forces
> the honouring of earlier store barriers.
I know I said I'd reached the end, but I have to point out that this
is certainly wrong.
A CAS is a Processor-local operation, and does not need to access
memory. The cache coherence protocol is sufficient. And a CAS
certainly is not guaranteed to do anything with any other stores.
On some processors it will; others not.
Andrew.