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Re: Proper use of x86/x86_64 CPUID instruction with extended assembler
- From: Jeffrey Walton <noloader at gmail dot com>
- To: Andrew Haley <aph at redhat dot com>
- Cc: "gcc-help at gcc dot gnu dot org" <gcc-help at gcc dot gnu dot org>
- Date: Wed, 19 Aug 2015 06:09:16 -0400
- Subject: Re: Proper use of x86/x86_64 CPUID instruction with extended assembler
- Authentication-results: sourceware.org; auth=none
- References: <CAH8yC8n9Vr3zeO0odOr3Jizv6vcO4o=s68OyPQwDa+ihaUMoNg at mail dot gmail dot com> <55D42400 dot 2060408 at cloudius-systems dot com> <CAH8yC8kkf5gWA-KWXFM=W6gKzYTzFdT3wcCkpBE8fRHLoc3xZg at mail dot gmail dot com> <55D43DCE dot 6080501 at cloudius-systems dot com> <CAH8yC8kyOtt4rUPXHw9qh+Aymsz2mZtJh9KKTh59F_aOSx-c5g at mail dot gmail dot com> <55D45398 dot 2040609 at redhat dot com>
- Reply-to: noloader at gmail dot com
>> According to Assembler Templates
>> (https://gcc.gnu.org/onlinedocs/gcc/Extended-Asm.html#AssemblerTemplate),
>> the save of the EBX register and the call to CPUID can be reordered,
>> even with volatile.
>
> No, it doesn't say that. It says that asm statements may not be
> consecutive. This is one asm statement.
>
Thanks Andrew. I parsed this incorrectly (I managed to invert it):
Do not expect a sequence of asm statements to remain
perfectly consecutive after compilation, even when you
are using the volatile qualifier. If certain instructions need
to remain consecutive in the output, put them in a single
multi-instruction asm statement.
Sorry about that.
Jeff