help for cache line alignment

[Alex Shi <alex dot shi at intel dot com>]

On Mon, 2012-03-05 at 11:43 +0100, Ingo Molnar wrote: 
> * Arnd Bergmann <arnd@arndb.de> wrote:
> 
> > On Monday 05 March 2012, Alex Shi wrote:
> > > Subject: [PATCH] lockdep: add cross cache lines checking
> > > 
> > > Modern x86 CPU won't hold whole memory bus when executing 
> > > 'lock' prefixed instructions unless the instruction 
> > > destination is crossing 2 cache lines. If so, it is disaster 
> > > of system performance.
> > > 
> > > Actually if the lock is not in the 'packed' structure, gcc 
> > > places it safely under x86 arch. But seems add this checking 
> > > in CONFIG_DEBUG_LOCK_ALLOC is harmless.
> > 
> > Have you tried making this a compile-time check using 
> > __alignof__? I would say that any spinlock in a packed data 
> > structure is basically a bug, even more so on most other 
> > architectures besides x86.

I have one concern and one questions here:
concern: maybe the lock is in a well designed 'packed' struct, and it is
safe for cross lines issue. but __alignof__ will return 1;

struct abc{
raw_spinlock_t lock1;
char a;
char b;
}__attribute__((packed));

Since the lock is the first object of struct, usually it is well placed.

question: I am a idiot on gcc, I tried some parameters of gcc " --param
l1-cache-line-size=1  -mno-align-double" and can not make a cross lines
variable without 'packed' structure, but I still don't find a grantee
why gcc can avoid the cross line variable if it's not in 'packed'
structure?