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Re: Disabling cache for some data
- From: John Love-Jensen <eljay at adobe dot com>
- To: Claudio Scordino <cloud dot of dot andor at gmail dot com>, MSX to GCC <gcc-help at gcc dot gnu dot org>
- Date: Fri, 20 Apr 2007 09:20:15 -0500
- Subject: Re: Disabling cache for some data
Hi Claudio,
What "cache" are you referring? In register optimization as a "cache"?
CPU's L1 cache? RAM's L2 cache? FSB L3 cache?
Is the memory array cache declared as volatile in the code?
Do you need to use a memory barrier to invalidate the cache?
HTH,
--Eljay