Question about RTL for bitwise AND

["Matt Lee" <reachmatt dot lee at gmail dot com>]

Hi,

 I am using powerpc-eabi-gcc (version 3.4.1) and I have a question
about the RTL that is produced for,

 test.c
 int a;

 if (a & 2) {
  // Do something
 } else
  // Do something else
 }


 I see in test.c.01.rtl,

 (insn 12 11 13 (set (reg:SI 122)
         (lshiftrt:SI (reg:SI 121)
             (const_int 1 [0x1]))) -1 (nil)
     (nil))

 (insn 13 12 14 (parallel [
             (set (reg:SI 123)
                 (and:SI (reg:SI 122)
                     (const_int 1 [0x1])))
             (clobber (scratch:CC))
         ]) -1 (nil)
     (nil))


 My question is, why is a logical shift right required? Wouldn't a
direct bit-wise AND with const_int 2 suffice?
 I am wondering if I am missing some C expression rules here? This
seems to be happening only for one-hot encoded bitwise ANDs.
 For e.g, if the expression is (a & 3), then I only see RTL generated
for the bitwise AND and there is no right shift. I am using -O3 -S as
compiler switches.
 I do see other architectures produce only the bitwise AND even for
one-hot encoded immediate operands such as 0x2.

 This is causing problems in my (other) port where I can do only
single-bit shifts. In the worst case, a & 0x80000000 the final
assembly contains 31 right shifts. This is a big optimization problem.

 Any advice is much helpful.

 thanks,
 Matt