RE: ELF instruction for section and branch.

["Gagneet Singh" <gagneet at acmet dot com>]

Hi!

Thanx for the answer.

So it would appear that we will not be able to generate ELF branch
across sections in MIPS architecture. But, is it possible for ELF
architecture as such, or 

"official ELF spec does not define a suitable relocation"

the above statement holds true for any architecture with ELF output. If
I wish to compile and link the example in the x86 architecture with ELF
format as output, how will I do that and specially is that possible??

Also, does GCC define sections in the assembly file as '.section .text1'
or is this example specific to an architecture??

Gagneet



> "Gagneet Singh" <gagneet@acmet.com> writes:
> > In your example,
> > "
> >>         .section .text1
> >> foo:    b        bar
> >> 
> >>         .section .text2
> >> bar:
> > "
> >
> > If we take "b  bar" as a 32-bit instruction, then to get the 
> > relocation information, of the label "bar", we can 
> calculate the 'bar' 
> > value using a 16-bit offset.
> >
> > If so, then it would be a 16-bit relocation.
> 
> Yes, but the point of what I said here:
> 
> >> It sounds like you're asking about code such as:
> >> 
> >>         .section .text1
> >> foo:    b        bar
> >> 
> >>         .section .text2
> >> bar:
> >> 
> >> Is that right?  If so, then no, this isn't supported.  The
> >> assembler can't calculate the branch offset because the 
> >> distance between foo and bar isn't known until link time.  
> >> And unfortunately, due to an infamous problem with the MIPS 
> >> ELF spec, there's no relocation that the assembler can use either.
> >> 
> >> (The R_MIPS_PC16 relocation was probably designed for
> >> branches, but the ELF spec says it gives a byte offset, 
> >> whereas branch instructions need a word offset.)
> 
> is that the official ELF spec does not define a suitable relocation.
> 
> Richard
>