This is the mail archive of the
gcc-help@gcc.gnu.org
mailing list for the GCC project.
Re: Register Spilling
- From: Falk Hueffner <falk dot hueffner at student dot uni-tuebingen dot de>
- To: Umar Janjua <Umar dot Janjua at cl dot cam dot ac dot uk>
- Cc: gcc-help at gcc dot gnu dot org
- Date: 10 Dec 2003 23:55:23 +0100
- Subject: Re: Register Spilling
- References: <E1AU64L-0002yd-00@wisbech.cl.cam.ac.uk>
Umar Janjua <Umar.Janjua@cl.cam.ac.uk> writes:
> Well, if that is the case, then , how advantageous would be
> considering cache locality for such register spilled values, so that
> instructions that require spilled values do not cause cache miss.
Most stack frames easily fit into L1, so probably not a lot. There has
been some work on this motivated by other things, though; see "Optimal
Stack Slot Assignment in GCC" by Naveen Sharma and Sanjiv Kumar Gupta
in the GCC summit proceedings
(http://www.linux.org.uk/~ajh/gcc/gccsummit-2003-proceedings.pdf)
--
Falk