[gcc r14-9282] alpha: Introduce UMUL_HIGHPART rtx_code [PR113720]

[Uros Bizjak]

https://gcc.gnu.org/g:318e0d44fe66ade59edb16a94565b3bfdc1883c6

commit r14-9282-g318e0d44fe66ade59edb16a94565b3bfdc1883c6
Author: Uros Bizjak <ubizjak@gmail.com>
Date:   Sun Mar 3 20:40:45 2024 +0100

    alpha: Introduce UMUL_HIGHPART rtx_code [PR113720]
    
    umuldi3_highpart expander does:
    
       if (REG_P (operands[2]))
         operands[2] = gen_rtx_ZERO_EXTEND (TImode, operands[2]);
    
    on register_operand predicate, which also allows SUBREG RTX. So,
    subregs were emitted without ZERO_EXTEND RTX.
    
    But nowadays we have UMUL_HIGHPART that allows us to fix this
    issue while also simplifying the instruction RTX.
    
            PR target/113720
    
    gcc/ChangeLog:
    
            * config/alpha/alpha.md (umuldi3_highpart): Remove expander.
            (*umuldi3_highpart_reg): Rename to umuldi3_highpart and
            simplify insn RTX using UMUL_HIGHPART rtx_code.
            (*umuldi3_highpart_const): Remove.

Diff:
---
 gcc/config/alpha/alpha.md | 37 +++----------------------------------
 1 file changed, 3 insertions(+), 34 deletions(-)

diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md
index 94d5d339c3d..79f12c53c16 100644
--- a/gcc/config/alpha/alpha.md
+++ b/gcc/config/alpha/alpha.md
@@ -683,41 +683,10 @@
   [(set_attr "type" "imul")
    (set_attr "opsize" "<mode>")])
 
-(define_expand "umuldi3_highpart"
-  [(set (match_operand:DI 0 "register_operand")
-	(truncate:DI
-	 (lshiftrt:TI
-	  (mult:TI (zero_extend:TI
-		     (match_operand:DI 1 "register_operand"))
-		   (match_operand:DI 2 "reg_or_8bit_operand"))
-	  (const_int 64))))]
-  ""
-{
-  if (REG_P (operands[2]))
-    operands[2] = gen_rtx_ZERO_EXTEND (TImode, operands[2]);
-})
-
-(define_insn "*umuldi3_highpart_reg"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(truncate:DI
-	 (lshiftrt:TI
-	  (mult:TI (zero_extend:TI
-		     (match_operand:DI 1 "register_operand" "r"))
-		   (zero_extend:TI
-		     (match_operand:DI 2 "register_operand" "r")))
-	  (const_int 64))))]
-  ""
-  "umulh %1,%2,%0"
-  [(set_attr "type" "imul")
-   (set_attr "opsize" "udi")])
-
-(define_insn "*umuldi3_highpart_const"
+(define_insn "umuldi3_highpart"
   [(set (match_operand:DI 0 "register_operand" "=r")
-	(truncate:DI
-	 (lshiftrt:TI
-	  (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
-		   (match_operand:TI 2 "cint8_operand" "I"))
-	  (const_int 64))))]
+	(umul_highpart:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
+			  (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
   ""
   "umulh %1,%2,%0"
   [(set_attr "type" "imul")