[gcc r14-4124] RISC-V: Support integer FMA/FNMA VLS modes autovectorization
Lehua Ding
lhtin@gcc.gnu.org
Tue Sep 19 08:17:19 GMT 2023
https://gcc.gnu.org/g:8e09480193ef870745f91f48a44ed0307757fb3c
commit r14-4124-g8e09480193ef870745f91f48a44ed0307757fb3c
Author: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date: Tue Sep 19 16:13:10 2023 +0800
RISC-V: Support integer FMA/FNMA VLS modes autovectorization
Simpily extend the current VLA iterator and patterns.
Regression passed with no difference.
gcc/ChangeLog:
* config/riscv/autovec.md: Add VLS modes.
* config/riscv/vector.md: Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls/def.h: Add VLS FMA/FNMA test.
* gcc.target/riscv/rvv/autovec/vls/fma-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/fma-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls/fma-3.c: New test.
* gcc.target/riscv/rvv/autovec/vls/fma-4.c: New test.
* gcc.target/riscv/rvv/autovec/vls/fnma-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/fnma-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls/fnma-3.c: New test.
* gcc.target/riscv/rvv/autovec/vls/fnma-4.c: New test.
Diff:
---
gcc/config/riscv/autovec.md | 24 +-
gcc/config/riscv/vector.md | 296 ++++++++++-----------
.../gcc.target/riscv/rvv/autovec/vls/def.h | 18 ++
.../gcc.target/riscv/rvv/autovec/vls/fma-1.c | 45 ++++
.../gcc.target/riscv/rvv/autovec/vls/fma-2.c | 43 +++
.../gcc.target/riscv/rvv/autovec/vls/fma-3.c | 41 +++
.../gcc.target/riscv/rvv/autovec/vls/fma-4.c | 39 +++
.../gcc.target/riscv/rvv/autovec/vls/fnma-1.c | 45 ++++
.../gcc.target/riscv/rvv/autovec/vls/fnma-2.c | 43 +++
.../gcc.target/riscv/rvv/autovec/vls/fnma-3.c | 41 +++
.../gcc.target/riscv/rvv/autovec/vls/fnma-4.c | 39 +++
11 files changed, 514 insertions(+), 160 deletions(-)
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index ac7599f3e0a..1aadb6eea1f 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -1079,12 +1079,12 @@
;; -------------------------------------------------------------------------
(define_insn_and_split "fma<mode>4"
- [(set (match_operand:VI 0 "register_operand")
- (plus:VI
- (mult:VI
- (match_operand:VI 1 "register_operand")
- (match_operand:VI 2 "register_operand"))
- (match_operand:VI 3 "register_operand")))]
+ [(set (match_operand:V_VLSI 0 "register_operand")
+ (plus:V_VLSI
+ (mult:V_VLSI
+ (match_operand:V_VLSI 1 "register_operand")
+ (match_operand:V_VLSI 2 "register_operand"))
+ (match_operand:V_VLSI 3 "register_operand")))]
"TARGET_VECTOR && can_create_pseudo_p ()"
"#"
"&& 1"
@@ -1107,12 +1107,12 @@
;; -------------------------------------------------------------------------
(define_insn_and_split "fnma<mode>4"
- [(set (match_operand:VI 0 "register_operand")
- (minus:VI
- (match_operand:VI 3 "register_operand")
- (mult:VI
- (match_operand:VI 1 "register_operand")
- (match_operand:VI 2 "register_operand"))))]
+ [(set (match_operand:V_VLSI 0 "register_operand")
+ (minus:V_VLSI
+ (match_operand:V_VLSI 3 "register_operand")
+ (mult:V_VLSI
+ (match_operand:V_VLSI 1 "register_operand")
+ (match_operand:V_VLSI 2 "register_operand"))))]
"TARGET_VECTOR && can_create_pseudo_p ()"
"#"
"&& 1"
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index c7c6ec3d6f1..c5a1c9061c4 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -5144,8 +5144,8 @@
;; -------------------------------------------------------------------------------
(define_expand "@pred_mul_plus<mode>"
- [(set (match_operand:VI 0 "register_operand")
- (if_then_else:VI
+ [(set (match_operand:V_VLSI 0 "register_operand")
+ (if_then_else:V_VLSI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand")
(match_operand 6 "vector_length_operand")
@@ -5154,20 +5154,20 @@
(match_operand 9 "const_int_operand")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (plus:VI
- (mult:VI
- (match_operand:VI 2 "register_operand")
- (match_operand:VI 3 "register_operand"))
- (match_operand:VI 4 "register_operand"))
- (match_operand:VI 5 "vector_merge_operand")))]
+ (plus:V_VLSI
+ (mult:V_VLSI
+ (match_operand:V_VLSI 2 "register_operand")
+ (match_operand:V_VLSI 3 "register_operand"))
+ (match_operand:V_VLSI 4 "register_operand"))
+ (match_operand:V_VLSI 5 "vector_merge_operand")))]
"TARGET_VECTOR"
{
riscv_vector::prepare_ternary_operands (operands);
})
(define_insn "*pred_mul_plus<mode>_undef"
- [(set (match_operand:VI 0 "register_operand" "=vd, vd,?&vd, vr, vr,?&vr")
- (if_then_else:VI
+ [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vd,?&vd, vr, vr,?&vr")
+ (if_then_else:V_VLSI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm, vm,Wc1,Wc1, Wc1")
(match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
@@ -5176,12 +5176,12 @@
(match_operand 9 "const_int_operand" " i, i, i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (plus:VI
- (mult:VI
- (match_operand:VI 3 "register_operand" " 0, vr, vr, 0, vr, vr")
- (match_operand:VI 4 "register_operand" " vr, vr, vr, vr, vr, vr"))
- (match_operand:VI 5 "register_operand" " vr, 0, vr, vr, 0, vr"))
- (match_operand:VI 2 "vector_undef_operand")))]
+ (plus:V_VLSI
+ (mult:V_VLSI
+ (match_operand:V_VLSI 3 "register_operand" " 0, vr, vr, 0, vr, vr")
+ (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr, vr, vr"))
+ (match_operand:V_VLSI 5 "register_operand" " vr, 0, vr, vr, 0, vr"))
+ (match_operand:V_VLSI 2 "vector_undef_operand")))]
"TARGET_VECTOR"
"@
vmadd.vv\t%0,%4,%5%p1
@@ -5194,8 +5194,8 @@
(set_attr "mode" "<MODE>")])
(define_insn "*pred_madd<mode>"
- [(set (match_operand:VI 0 "register_operand" "=vd,?&vd, vr,?&vr")
- (if_then_else:VI
+ [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr")
+ (if_then_else:V_VLSI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
(match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
@@ -5204,11 +5204,11 @@
(match_operand 8 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (plus:VI
- (mult:VI
- (match_operand:VI 2 "register_operand" " 0, vr, 0, vr")
- (match_operand:VI 3 "register_operand" " vr, vr, vr, vr"))
- (match_operand:VI 4 "register_operand" " vr, vr, vr, vr"))
+ (plus:V_VLSI
+ (mult:V_VLSI
+ (match_operand:V_VLSI 2 "register_operand" " 0, vr, 0, vr")
+ (match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr"))
+ (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr"))
(match_dup 2)))]
"TARGET_VECTOR"
"@
@@ -5225,8 +5225,8 @@
(set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
(define_insn "*pred_macc<mode>"
- [(set (match_operand:VI 0 "register_operand" "=vd,?&vd, vr,?&vr")
- (if_then_else:VI
+ [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr")
+ (if_then_else:V_VLSI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
(match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
@@ -5235,11 +5235,11 @@
(match_operand 8 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (plus:VI
- (mult:VI
- (match_operand:VI 2 "register_operand" " vr, vr, vr, vr")
- (match_operand:VI 3 "register_operand" " vr, vr, vr, vr"))
- (match_operand:VI 4 "register_operand" " 0, vr, 0, vr"))
+ (plus:V_VLSI
+ (mult:V_VLSI
+ (match_operand:V_VLSI 2 "register_operand" " vr, vr, vr, vr")
+ (match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr"))
+ (match_operand:V_VLSI 4 "register_operand" " 0, vr, 0, vr"))
(match_dup 4)))]
"TARGET_VECTOR"
"@
@@ -5256,8 +5256,8 @@
(set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
(define_expand "@pred_mul_plus<mode>_scalar"
- [(set (match_operand:VI_QHS 0 "register_operand")
- (if_then_else:VI_QHS
+ [(set (match_operand:V_VLSI_QHS 0 "register_operand")
+ (if_then_else:V_VLSI_QHS
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand")
(match_operand 6 "vector_length_operand")
@@ -5266,19 +5266,19 @@
(match_operand 9 "const_int_operand")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (plus:VI_QHS
- (mult:VI_QHS
- (vec_duplicate:VI_QHS
+ (plus:V_VLSI_QHS
+ (mult:V_VLSI_QHS
+ (vec_duplicate:V_VLSI_QHS
(match_operand:<VEL> 2 "register_operand"))
- (match_operand:VI_QHS 3 "register_operand"))
- (match_operand:VI_QHS 4 "register_operand"))
- (match_operand:VI_QHS 5 "register_operand")))]
+ (match_operand:V_VLSI_QHS 3 "register_operand"))
+ (match_operand:V_VLSI_QHS 4 "register_operand"))
+ (match_operand:V_VLSI_QHS 5 "register_operand")))]
"TARGET_VECTOR"
{})
(define_insn "*pred_madd<mode>_scalar"
- [(set (match_operand:VI 0 "register_operand" "=vd,?&vd, vr,?&vr")
- (if_then_else:VI
+ [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr")
+ (if_then_else:V_VLSI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
(match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
@@ -5287,12 +5287,12 @@
(match_operand 8 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (plus:VI
- (mult:VI
- (vec_duplicate:VI
+ (plus:V_VLSI
+ (mult:V_VLSI
+ (vec_duplicate:V_VLSI
(match_operand:<VEL> 2 "register_operand" " r, r, r, r"))
- (match_operand:VI 3 "register_operand" " 0, vr, 0, vr"))
- (match_operand:VI 4 "register_operand" " vr, vr, vr, vr"))
+ (match_operand:V_VLSI 3 "register_operand" " 0, vr, 0, vr"))
+ (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr"))
(match_dup 3)))]
"TARGET_VECTOR"
"@
@@ -5309,8 +5309,8 @@
(set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
(define_insn "*pred_macc<mode>_scalar"
- [(set (match_operand:VI 0 "register_operand" "=vd,?&vd, vr,?&vr")
- (if_then_else:VI
+ [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr")
+ (if_then_else:V_VLSI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
(match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
@@ -5319,12 +5319,12 @@
(match_operand 8 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (plus:VI
- (mult:VI
- (vec_duplicate:VI
+ (plus:V_VLSI
+ (mult:V_VLSI
+ (vec_duplicate:V_VLSI
(match_operand:<VEL> 2 "register_operand" " r, r, r, r"))
- (match_operand:VI 3 "register_operand" " vr, vr, vr, vr"))
- (match_operand:VI 4 "register_operand" " 0, vr, 0, vr"))
+ (match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr"))
+ (match_operand:V_VLSI 4 "register_operand" " 0, vr, 0, vr"))
(match_dup 4)))]
"TARGET_VECTOR"
"@
@@ -5341,8 +5341,8 @@
(set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
(define_expand "@pred_mul_plus<mode>_scalar"
- [(set (match_operand:VI_D 0 "register_operand")
- (if_then_else:VI_D
+ [(set (match_operand:V_VLSI_D 0 "register_operand")
+ (if_then_else:V_VLSI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand")
(match_operand 6 "vector_length_operand")
@@ -5351,13 +5351,13 @@
(match_operand 9 "const_int_operand")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (plus:VI_D
- (mult:VI_D
- (vec_duplicate:VI_D
+ (plus:V_VLSI_D
+ (mult:V_VLSI_D
+ (vec_duplicate:V_VLSI_D
(match_operand:<VEL> 2 "reg_or_int_operand"))
- (match_operand:VI_D 3 "register_operand"))
- (match_operand:VI_D 4 "register_operand"))
- (match_operand:VI_D 5 "register_operand")))]
+ (match_operand:V_VLSI_D 3 "register_operand"))
+ (match_operand:V_VLSI_D 4 "register_operand"))
+ (match_operand:V_VLSI_D 5 "register_operand")))]
"TARGET_VECTOR"
{
if (riscv_vector::sew64_scalar_helper (
@@ -5375,8 +5375,8 @@
})
(define_insn "*pred_madd<mode>_extended_scalar"
- [(set (match_operand:VI_D 0 "register_operand" "=vd,?&vd, vr,?&vr")
- (if_then_else:VI_D
+ [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,?&vd, vr,?&vr")
+ (if_then_else:V_VLSI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
(match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
@@ -5385,13 +5385,13 @@
(match_operand 8 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (plus:VI_D
- (mult:VI_D
- (vec_duplicate:VI_D
+ (plus:V_VLSI_D
+ (mult:V_VLSI_D
+ (vec_duplicate:V_VLSI_D
(sign_extend:<VEL>
(match_operand:<VSUBEL> 2 "register_operand" " r, r, r, r")))
- (match_operand:VI_D 3 "register_operand" " 0, vr, 0, vr"))
- (match_operand:VI_D 4 "register_operand" " vr, vr, vr, vr"))
+ (match_operand:V_VLSI_D 3 "register_operand" " 0, vr, 0, vr"))
+ (match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr"))
(match_dup 3)))]
"TARGET_VECTOR"
"@
@@ -5408,8 +5408,8 @@
(set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
(define_insn "*pred_macc<mode>_extended_scalar"
- [(set (match_operand:VI_D 0 "register_operand" "=vd,?&vd, vr,?&vr")
- (if_then_else:VI_D
+ [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,?&vd, vr,?&vr")
+ (if_then_else:V_VLSI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
(match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
@@ -5418,13 +5418,13 @@
(match_operand 8 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (plus:VI_D
- (mult:VI_D
- (vec_duplicate:VI_D
+ (plus:V_VLSI_D
+ (mult:V_VLSI_D
+ (vec_duplicate:V_VLSI_D
(sign_extend:<VEL>
(match_operand:<VSUBEL> 2 "register_operand" " r, r, r, r")))
- (match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr"))
- (match_operand:VI_D 4 "register_operand" " 0, vr, 0, vr"))
+ (match_operand:V_VLSI_D 3 "register_operand" " vr, vr, vr, vr"))
+ (match_operand:V_VLSI_D 4 "register_operand" " 0, vr, 0, vr"))
(match_dup 4)))]
"TARGET_VECTOR"
"@
@@ -5441,8 +5441,8 @@
(set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
(define_expand "@pred_minus_mul<mode>"
- [(set (match_operand:VI 0 "register_operand")
- (if_then_else:VI
+ [(set (match_operand:V_VLSI 0 "register_operand")
+ (if_then_else:V_VLSI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand")
(match_operand 6 "vector_length_operand")
@@ -5451,20 +5451,20 @@
(match_operand 9 "const_int_operand")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (minus:VI
- (match_operand:VI 4 "register_operand")
- (mult:VI
- (match_operand:VI 2 "register_operand")
- (match_operand:VI 3 "register_operand")))
- (match_operand:VI 5 "vector_merge_operand")))]
+ (minus:V_VLSI
+ (match_operand:V_VLSI 4 "register_operand")
+ (mult:V_VLSI
+ (match_operand:V_VLSI 2 "register_operand")
+ (match_operand:V_VLSI 3 "register_operand")))
+ (match_operand:V_VLSI 5 "vector_merge_operand")))]
"TARGET_VECTOR"
{
riscv_vector::prepare_ternary_operands (operands);
})
(define_insn "*pred_minus_mul<mode>_undef"
- [(set (match_operand:VI 0 "register_operand" "=vd, vd,?&vd, vr, vr,?&vr")
- (if_then_else:VI
+ [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vd,?&vd, vr, vr,?&vr")
+ (if_then_else:V_VLSI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm, vm,Wc1,Wc1, Wc1")
(match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
@@ -5473,12 +5473,12 @@
(match_operand 9 "const_int_operand" " i, i, i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (minus:VI
- (match_operand:VI 5 "register_operand" " vr, 0, vr, vr, 0, vr")
- (mult:VI
- (match_operand:VI 3 "register_operand" " 0, vr, vr, 0, vr, vr")
- (match_operand:VI 4 "register_operand" " vr, vr, vr, vr, vr, vr")))
- (match_operand:VI 2 "vector_undef_operand")))]
+ (minus:V_VLSI
+ (match_operand:V_VLSI 5 "register_operand" " vr, 0, vr, vr, 0, vr")
+ (mult:V_VLSI
+ (match_operand:V_VLSI 3 "register_operand" " 0, vr, vr, 0, vr, vr")
+ (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr, vr, vr")))
+ (match_operand:V_VLSI 2 "vector_undef_operand")))]
"TARGET_VECTOR"
"@
vnmsub.vv\t%0,%4,%5%p1
@@ -5491,8 +5491,8 @@
(set_attr "mode" "<MODE>")])
(define_insn "*pred_nmsub<mode>"
- [(set (match_operand:VI 0 "register_operand" "=vd,?&vd, vr,?&vr")
- (if_then_else:VI
+ [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr")
+ (if_then_else:V_VLSI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
(match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
@@ -5501,11 +5501,11 @@
(match_operand 8 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (minus:VI
- (match_operand:VI 4 "register_operand" " vr, vr, vr, vr")
- (mult:VI
- (match_operand:VI 2 "register_operand" " 0, vr, 0, vr")
- (match_operand:VI 3 "register_operand" " vr, vr, vr, vr")))
+ (minus:V_VLSI
+ (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr")
+ (mult:V_VLSI
+ (match_operand:V_VLSI 2 "register_operand" " 0, vr, 0, vr")
+ (match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr")))
(match_dup 2)))]
"TARGET_VECTOR"
"@
@@ -5522,8 +5522,8 @@
(set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
(define_insn "*pred_nmsac<mode>"
- [(set (match_operand:VI 0 "register_operand" "=vd,?&vd, vr,?&vr")
- (if_then_else:VI
+ [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr")
+ (if_then_else:V_VLSI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
(match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
@@ -5532,11 +5532,11 @@
(match_operand 8 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (minus:VI
- (match_operand:VI 4 "register_operand" " 0, vr, 0, vr")
- (mult:VI
- (match_operand:VI 2 "register_operand" " vr, vr, vr, vr")
- (match_operand:VI 3 "register_operand" " vr, vr, vr, vr")))
+ (minus:V_VLSI
+ (match_operand:V_VLSI 4 "register_operand" " 0, vr, 0, vr")
+ (mult:V_VLSI
+ (match_operand:V_VLSI 2 "register_operand" " vr, vr, vr, vr")
+ (match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr")))
(match_dup 4)))]
"TARGET_VECTOR"
"@
@@ -5553,8 +5553,8 @@
(set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
(define_expand "@pred_minus_mul<mode>_scalar"
- [(set (match_operand:VI_QHS 0 "register_operand")
- (if_then_else:VI_QHS
+ [(set (match_operand:V_VLSI_QHS 0 "register_operand")
+ (if_then_else:V_VLSI_QHS
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand")
(match_operand 6 "vector_length_operand")
@@ -5563,19 +5563,19 @@
(match_operand 9 "const_int_operand")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (minus:VI_QHS
- (match_operand:VI_QHS 4 "register_operand")
- (mult:VI_QHS
- (vec_duplicate:VI_QHS
+ (minus:V_VLSI_QHS
+ (match_operand:V_VLSI_QHS 4 "register_operand")
+ (mult:V_VLSI_QHS
+ (vec_duplicate:V_VLSI_QHS
(match_operand:<VEL> 2 "register_operand"))
- (match_operand:VI_QHS 3 "register_operand")))
- (match_operand:VI_QHS 5 "register_operand")))]
+ (match_operand:V_VLSI_QHS 3 "register_operand")))
+ (match_operand:V_VLSI_QHS 5 "register_operand")))]
"TARGET_VECTOR"
{})
(define_insn "*pred_nmsub<mode>_scalar"
- [(set (match_operand:VI 0 "register_operand" "=vd,?&vd, vr,?&vr")
- (if_then_else:VI
+ [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr")
+ (if_then_else:V_VLSI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
(match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
@@ -5584,12 +5584,12 @@
(match_operand 8 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (minus:VI
- (match_operand:VI 4 "register_operand" " vr, vr, vr, vr")
- (mult:VI
- (vec_duplicate:VI
+ (minus:V_VLSI
+ (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr")
+ (mult:V_VLSI
+ (vec_duplicate:V_VLSI
(match_operand:<VEL> 2 "register_operand" " r, r, r, r"))
- (match_operand:VI 3 "register_operand" " 0, vr, 0, vr")))
+ (match_operand:V_VLSI 3 "register_operand" " 0, vr, 0, vr")))
(match_dup 3)))]
"TARGET_VECTOR"
"@
@@ -5606,8 +5606,8 @@
(set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
(define_insn "*pred_nmsac<mode>_scalar"
- [(set (match_operand:VI 0 "register_operand" "=vd,?&vd, vr,?&vr")
- (if_then_else:VI
+ [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr")
+ (if_then_else:V_VLSI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
(match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
@@ -5616,12 +5616,12 @@
(match_operand 8 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (minus:VI
- (match_operand:VI 4 "register_operand" " 0, vr, 0, vr")
- (mult:VI
- (vec_duplicate:VI
+ (minus:V_VLSI
+ (match_operand:V_VLSI 4 "register_operand" " 0, vr, 0, vr")
+ (mult:V_VLSI
+ (vec_duplicate:V_VLSI
(match_operand:<VEL> 2 "register_operand" " r, r, r, r"))
- (match_operand:VI 3 "register_operand" " vr, vr, vr, vr")))
+ (match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr")))
(match_dup 4)))]
"TARGET_VECTOR"
"@
@@ -5638,8 +5638,8 @@
(set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
(define_expand "@pred_minus_mul<mode>_scalar"
- [(set (match_operand:VI_D 0 "register_operand")
- (if_then_else:VI_D
+ [(set (match_operand:V_VLSI_D 0 "register_operand")
+ (if_then_else:V_VLSI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand")
(match_operand 6 "vector_length_operand")
@@ -5648,13 +5648,13 @@
(match_operand 9 "const_int_operand")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (minus:VI_D
- (match_operand:VI_D 4 "register_operand")
- (mult:VI_D
- (vec_duplicate:VI_D
+ (minus:V_VLSI_D
+ (match_operand:V_VLSI_D 4 "register_operand")
+ (mult:V_VLSI_D
+ (vec_duplicate:V_VLSI_D
(match_operand:<VEL> 2 "reg_or_int_operand"))
- (match_operand:VI_D 3 "register_operand")))
- (match_operand:VI_D 5 "register_operand")))]
+ (match_operand:V_VLSI_D 3 "register_operand")))
+ (match_operand:V_VLSI_D 5 "register_operand")))]
"TARGET_VECTOR"
{
if (riscv_vector::sew64_scalar_helper (
@@ -5672,8 +5672,8 @@
})
(define_insn "*pred_nmsub<mode>_extended_scalar"
- [(set (match_operand:VI_D 0 "register_operand" "=vd,?&vd, vr,?&vr")
- (if_then_else:VI_D
+ [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,?&vd, vr,?&vr")
+ (if_then_else:V_VLSI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
(match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
@@ -5682,13 +5682,13 @@
(match_operand 8 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (minus:VI_D
- (match_operand:VI_D 4 "register_operand" " vr, vr, vr, vr")
- (mult:VI_D
- (vec_duplicate:VI_D
+ (minus:V_VLSI_D
+ (match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr")
+ (mult:V_VLSI_D
+ (vec_duplicate:V_VLSI_D
(sign_extend:<VEL>
(match_operand:<VSUBEL> 2 "register_operand" " r, r, r, r")))
- (match_operand:VI_D 3 "register_operand" " 0, vr, 0, vr")))
+ (match_operand:V_VLSI_D 3 "register_operand" " 0, vr, 0, vr")))
(match_dup 3)))]
"TARGET_VECTOR"
"@
@@ -5705,8 +5705,8 @@
(set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
(define_insn "*pred_nmsac<mode>_extended_scalar"
- [(set (match_operand:VI_D 0 "register_operand" "=vd,?&vd, vr,?&vr")
- (if_then_else:VI_D
+ [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,?&vd, vr,?&vr")
+ (if_then_else:V_VLSI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
(match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
@@ -5715,13 +5715,13 @@
(match_operand 8 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (minus:VI_D
- (match_operand:VI_D 4 "register_operand" " 0, vr, 0, vr")
- (mult:VI_D
- (vec_duplicate:VI_D
+ (minus:V_VLSI_D
+ (match_operand:V_VLSI_D 4 "register_operand" " 0, vr, 0, vr")
+ (mult:V_VLSI_D
+ (vec_duplicate:V_VLSI_D
(sign_extend:<VEL>
(match_operand:<VSUBEL> 2 "register_operand" " r, r, r, r")))
- (match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr")))
+ (match_operand:V_VLSI_D 3 "register_operand" " vr, vr, vr, vr")))
(match_dup 4)))]
"TARGET_VECTOR"
"@
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
index 4d32de5a61f..7528ee73d9e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
@@ -457,3 +457,21 @@ typedef double v512df __attribute__ ((vector_size (4096)));
\
return v; \
}
+
+#define DEF_FMA_VV(PREFIX, NUM, TYPE) \
+ void __attribute__ ((noinline, noclone)) \
+ PREFIX##_##TYPE##NUM (TYPE *restrict a, TYPE *restrict b, TYPE *restrict c, \
+ TYPE *restrict d) \
+ { \
+ for (int i = 0; i < NUM; ++i) \
+ a[i] = b[i] * c[i] + d[i]; \
+ }
+
+#define DEF_FNMA_VV(PREFIX, NUM, TYPE) \
+ void __attribute__ ((noinline, noclone)) \
+ PREFIX##_##TYPE##NUM (TYPE *restrict a, TYPE *restrict b, TYPE *restrict c, \
+ TYPE *restrict d) \
+ { \
+ for (int i = 0; i < NUM; ++i) \
+ a[i] = d[i] - b[i] * c[i]; \
+ }
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-1.c
new file mode 100644
index 00000000000..7f9073a4dc1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-1.c
@@ -0,0 +1,45 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_FMA_VV (fma, 2, int8_t)
+DEF_FMA_VV (fma, 4, int8_t)
+DEF_FMA_VV (fma, 8, int8_t)
+DEF_FMA_VV (fma, 16, int8_t)
+DEF_FMA_VV (fma, 32, int8_t)
+DEF_FMA_VV (fma, 64, int8_t)
+DEF_FMA_VV (fma, 128, int8_t)
+DEF_FMA_VV (fma, 256, int8_t)
+DEF_FMA_VV (fma, 512, int8_t)
+DEF_FMA_VV (fma, 1024, int8_t)
+DEF_FMA_VV (fma, 2048, int8_t)
+DEF_FMA_VV (fma, 4096, int8_t)
+
+DEF_FMA_VV (fma, 2, uint8_t)
+DEF_FMA_VV (fma, 4, uint8_t)
+DEF_FMA_VV (fma, 8, uint8_t)
+DEF_FMA_VV (fma, 16, uint8_t)
+DEF_FMA_VV (fma, 32, uint8_t)
+DEF_FMA_VV (fma, 64, uint8_t)
+DEF_FMA_VV (fma, 128, uint8_t)
+DEF_FMA_VV (fma, 256, uint8_t)
+DEF_FMA_VV (fma, 512, uint8_t)
+DEF_FMA_VV (fma, 1024, uint8_t)
+DEF_FMA_VV (fma, 2048, uint8_t)
+DEF_FMA_VV (fma, 4096, uint8_t)
+
+/* { dg-final { scan-assembler-times {vma[c-d][c-d]\.vv} 24 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-2.c
new file mode 100644
index 00000000000..ddc4b552fc7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-2.c
@@ -0,0 +1,43 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_FMA_VV (fma, 2, int16_t)
+DEF_FMA_VV (fma, 4, int16_t)
+DEF_FMA_VV (fma, 8, int16_t)
+DEF_FMA_VV (fma, 16, int16_t)
+DEF_FMA_VV (fma, 32, int16_t)
+DEF_FMA_VV (fma, 64, int16_t)
+DEF_FMA_VV (fma, 128, int16_t)
+DEF_FMA_VV (fma, 256, int16_t)
+DEF_FMA_VV (fma, 512, int16_t)
+DEF_FMA_VV (fma, 1024, int16_t)
+DEF_FMA_VV (fma, 2048, int16_t)
+
+DEF_FMA_VV (fma, 2, uint16_t)
+DEF_FMA_VV (fma, 4, uint16_t)
+DEF_FMA_VV (fma, 8, uint16_t)
+DEF_FMA_VV (fma, 16, uint16_t)
+DEF_FMA_VV (fma, 32, uint16_t)
+DEF_FMA_VV (fma, 64, uint16_t)
+DEF_FMA_VV (fma, 128, uint16_t)
+DEF_FMA_VV (fma, 256, uint16_t)
+DEF_FMA_VV (fma, 512, uint16_t)
+DEF_FMA_VV (fma, 1024, uint16_t)
+DEF_FMA_VV (fma, 2048, uint16_t)
+
+/* { dg-final { scan-assembler-times {vma[c-d][c-d]\.vv} 22 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-3.c
new file mode 100644
index 00000000000..3bb52ae5974
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-3.c
@@ -0,0 +1,41 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_FMA_VV (fma, 2, int32_t)
+DEF_FMA_VV (fma, 4, int32_t)
+DEF_FMA_VV (fma, 8, int32_t)
+DEF_FMA_VV (fma, 16, int32_t)
+DEF_FMA_VV (fma, 32, int32_t)
+DEF_FMA_VV (fma, 64, int32_t)
+DEF_FMA_VV (fma, 128, int32_t)
+DEF_FMA_VV (fma, 256, int32_t)
+DEF_FMA_VV (fma, 512, int32_t)
+DEF_FMA_VV (fma, 1024, int32_t)
+
+DEF_FMA_VV (fma, 2, uint32_t)
+DEF_FMA_VV (fma, 4, uint32_t)
+DEF_FMA_VV (fma, 8, uint32_t)
+DEF_FMA_VV (fma, 16, uint32_t)
+DEF_FMA_VV (fma, 32, uint32_t)
+DEF_FMA_VV (fma, 64, uint32_t)
+DEF_FMA_VV (fma, 128, uint32_t)
+DEF_FMA_VV (fma, 256, uint32_t)
+DEF_FMA_VV (fma, 512, uint32_t)
+DEF_FMA_VV (fma, 1024, uint32_t)
+
+/* { dg-final { scan-assembler-times {vma[c-d][c-d]\.vv} 20 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-4.c
new file mode 100644
index 00000000000..903a4f723e6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-4.c
@@ -0,0 +1,39 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_FMA_VV (fma, 2, int64_t)
+DEF_FMA_VV (fma, 4, int64_t)
+DEF_FMA_VV (fma, 8, int64_t)
+DEF_FMA_VV (fma, 16, int64_t)
+DEF_FMA_VV (fma, 32, int64_t)
+DEF_FMA_VV (fma, 64, int64_t)
+DEF_FMA_VV (fma, 128, int64_t)
+DEF_FMA_VV (fma, 256, int64_t)
+DEF_FMA_VV (fma, 512, int64_t)
+
+DEF_FMA_VV (fma, 2, uint64_t)
+DEF_FMA_VV (fma, 4, uint64_t)
+DEF_FMA_VV (fma, 8, uint64_t)
+DEF_FMA_VV (fma, 16, uint64_t)
+DEF_FMA_VV (fma, 32, uint64_t)
+DEF_FMA_VV (fma, 64, uint64_t)
+DEF_FMA_VV (fma, 128, uint64_t)
+DEF_FMA_VV (fma, 256, uint64_t)
+DEF_FMA_VV (fma, 512, uint64_t)
+
+/* { dg-final { scan-assembler-times {vma[c-d][c-d]\.vv} 18 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-1.c
new file mode 100644
index 00000000000..418c767a7bf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-1.c
@@ -0,0 +1,45 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_FNMA_VV (fnma, 2, int8_t)
+DEF_FNMA_VV (fnma, 4, int8_t)
+DEF_FNMA_VV (fnma, 8, int8_t)
+DEF_FNMA_VV (fnma, 16, int8_t)
+DEF_FNMA_VV (fnma, 32, int8_t)
+DEF_FNMA_VV (fnma, 64, int8_t)
+DEF_FNMA_VV (fnma, 128, int8_t)
+DEF_FNMA_VV (fnma, 256, int8_t)
+DEF_FNMA_VV (fnma, 512, int8_t)
+DEF_FNMA_VV (fnma, 1024, int8_t)
+DEF_FNMA_VV (fnma, 2048, int8_t)
+DEF_FNMA_VV (fnma, 4096, int8_t)
+
+DEF_FNMA_VV (fnma, 2, uint8_t)
+DEF_FNMA_VV (fnma, 4, uint8_t)
+DEF_FNMA_VV (fnma, 8, uint8_t)
+DEF_FNMA_VV (fnma, 16, uint8_t)
+DEF_FNMA_VV (fnma, 32, uint8_t)
+DEF_FNMA_VV (fnma, 64, uint8_t)
+DEF_FNMA_VV (fnma, 128, uint8_t)
+DEF_FNMA_VV (fnma, 256, uint8_t)
+DEF_FNMA_VV (fnma, 512, uint8_t)
+DEF_FNMA_VV (fnma, 1024, uint8_t)
+DEF_FNMA_VV (fnma, 2048, uint8_t)
+DEF_FNMA_VV (fnma, 4096, uint8_t)
+
+/* { dg-final { scan-assembler-times {vnms[a-u][b-c]\.vv} 24 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-2.c
new file mode 100644
index 00000000000..c1b629a7b22
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-2.c
@@ -0,0 +1,43 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_FNMA_VV (fnma, 2, int16_t)
+DEF_FNMA_VV (fnma, 4, int16_t)
+DEF_FNMA_VV (fnma, 8, int16_t)
+DEF_FNMA_VV (fnma, 16, int16_t)
+DEF_FNMA_VV (fnma, 32, int16_t)
+DEF_FNMA_VV (fnma, 64, int16_t)
+DEF_FNMA_VV (fnma, 128, int16_t)
+DEF_FNMA_VV (fnma, 256, int16_t)
+DEF_FNMA_VV (fnma, 512, int16_t)
+DEF_FNMA_VV (fnma, 1024, int16_t)
+DEF_FNMA_VV (fnma, 2048, int16_t)
+
+DEF_FNMA_VV (fnma, 2, uint16_t)
+DEF_FNMA_VV (fnma, 4, uint16_t)
+DEF_FNMA_VV (fnma, 8, uint16_t)
+DEF_FNMA_VV (fnma, 16, uint16_t)
+DEF_FNMA_VV (fnma, 32, uint16_t)
+DEF_FNMA_VV (fnma, 64, uint16_t)
+DEF_FNMA_VV (fnma, 128, uint16_t)
+DEF_FNMA_VV (fnma, 256, uint16_t)
+DEF_FNMA_VV (fnma, 512, uint16_t)
+DEF_FNMA_VV (fnma, 1024, uint16_t)
+DEF_FNMA_VV (fnma, 2048, uint16_t)
+
+/* { dg-final { scan-assembler-times {vnms[a-u][b-c]\.vv} 22 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-3.c
new file mode 100644
index 00000000000..bab693eda0b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-3.c
@@ -0,0 +1,41 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_FNMA_VV (fnma, 2, int32_t)
+DEF_FNMA_VV (fnma, 4, int32_t)
+DEF_FNMA_VV (fnma, 8, int32_t)
+DEF_FNMA_VV (fnma, 16, int32_t)
+DEF_FNMA_VV (fnma, 32, int32_t)
+DEF_FNMA_VV (fnma, 64, int32_t)
+DEF_FNMA_VV (fnma, 128, int32_t)
+DEF_FNMA_VV (fnma, 256, int32_t)
+DEF_FNMA_VV (fnma, 512, int32_t)
+DEF_FNMA_VV (fnma, 1024, int32_t)
+
+DEF_FNMA_VV (fnma, 2, uint32_t)
+DEF_FNMA_VV (fnma, 4, uint32_t)
+DEF_FNMA_VV (fnma, 8, uint32_t)
+DEF_FNMA_VV (fnma, 16, uint32_t)
+DEF_FNMA_VV (fnma, 32, uint32_t)
+DEF_FNMA_VV (fnma, 64, uint32_t)
+DEF_FNMA_VV (fnma, 128, uint32_t)
+DEF_FNMA_VV (fnma, 256, uint32_t)
+DEF_FNMA_VV (fnma, 512, uint32_t)
+DEF_FNMA_VV (fnma, 1024, uint32_t)
+
+/* { dg-final { scan-assembler-times {vnms[a-u][b-c]\.vv} 20 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-4.c
new file mode 100644
index 00000000000..f0a7c5dee30
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-4.c
@@ -0,0 +1,39 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_FNMA_VV (fnma, 2, int64_t)
+DEF_FNMA_VV (fnma, 4, int64_t)
+DEF_FNMA_VV (fnma, 8, int64_t)
+DEF_FNMA_VV (fnma, 16, int64_t)
+DEF_FNMA_VV (fnma, 32, int64_t)
+DEF_FNMA_VV (fnma, 64, int64_t)
+DEF_FNMA_VV (fnma, 128, int64_t)
+DEF_FNMA_VV (fnma, 256, int64_t)
+DEF_FNMA_VV (fnma, 512, int64_t)
+
+DEF_FNMA_VV (fnma, 2, uint64_t)
+DEF_FNMA_VV (fnma, 4, uint64_t)
+DEF_FNMA_VV (fnma, 8, uint64_t)
+DEF_FNMA_VV (fnma, 16, uint64_t)
+DEF_FNMA_VV (fnma, 32, uint64_t)
+DEF_FNMA_VV (fnma, 64, uint64_t)
+DEF_FNMA_VV (fnma, 128, uint64_t)
+DEF_FNMA_VV (fnma, 256, uint64_t)
+DEF_FNMA_VV (fnma, 512, uint64_t)
+
+/* { dg-final { scan-assembler-times {vnms[a-u][b-c]\.vv} 18 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
More information about the Gcc-cvs
mailing list