[gcc/meissner/heads/work114-orig] (20 commits) Merge commit 'refs/users/meissner/heads/work114-orig' of gi

[Michael Meissner]

The branch 'meissner/heads/work114-orig' was updated to point to:

 73f0e2ab409... Merge commit 'refs/users/meissner/heads/work114-orig' of gi

It previously pointed to:

 eab4a1d96c7... Add REVISION.

Diff:

Summary of changes (added commits):
-----------------------------------

  73f0e2a... Merge commit 'refs/users/meissner/heads/work114-orig' of gi
  9ae9650... Add REVISION.
  80ed2a6... c: [PR84900] cast of compound literal does not cause the co (*)
  5ededfa... PR modula2/109264 Bugfix resolve opaque types containing se (*)
  41ade33... tree-optimization/107569 - avoid wrecking earlier folding i (*)
  25979b6... tree-optimization/109262 - ICE with non-call EH and forwpro (*)
  c46b5b0... ranger: Ranger meets aspell (*)
  097e2af... Skip gnat.dg/div_zero.adb on Aarch64 (*)
  59bfdd5... c++: further -Wdangling-reference refinement [PR107532] (*)
  3b97715... amdgcn: Fix register size bug (*)
  db80ccd... amdgcn: vec_extract no-op insns (*)
  484c41c... tree-vect-generic: Fix up expand_vector_condition [PR109176 (*)
  3a982e0... RISC-V: Bugfix for rvv bool mode size adjustment (*)
  37dd1f1... RISC-V: Fix loss of function to script 'multilib-generator' (*)
  4872e46... c++: local class in nested generic lambda [PR109241] (*)
  cd0c433... RISC-V: Fix LRA issue for LMUL < 1 vector spillings [PR1092 (*)
  116a867... RISC-V: Implement __riscv_vlenb PR109228 (*)
  a481eed... RISC-V: Fix wrong vsetvli fusion for vmv.s.x (*)
  0e27151... RISC-V: Fix wrong RTL pattern for ternary instructions. (*)
  ba31f9a... RISC-V: Add riscv_vector target check (*)

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