[gcc(refs/users/meissner/heads/work122-dmf)] Revert patches
Michael Meissner
meissner@gcc.gnu.org
Wed Jun 14 19:42:44 GMT 2023
https://gcc.gnu.org/g:e789079eda45024ac06ca4af230830e32f4aa52a
commit e789079eda45024ac06ca4af230830e32f4aa52a
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Jun 14 15:42:41 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/mma.md | 247 ++++++++++++++++--------------------------
gcc/config/rs6000/rs6000-c.cc | 3 -
gcc/config/rs6000/rs6000.cc | 35 +++---
3 files changed, 109 insertions(+), 176 deletions(-)
diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md
index 9e3feb3ea54..59ca6835f7c 100644
--- a/gcc/config/rs6000/mma.md
+++ b/gcc/config/rs6000/mma.md
@@ -552,249 +552,190 @@
"dmxxextfdmr256 %0,%1,2"
[(set_attr "type" "mma")])
-;; MMA instructions that do not use their accumulators as an input, still must
-;; not allow their vector operands to overlap the registers used by the
-;; accumulator. We enforce this by marking the output as early clobber. If we
-;; have dense math, we don't need the whole prime/de-prime action, so just make
-;; thse instructions be NOPs.
-
-(define_expand "mma_<acc>"
- [(set (match_operand:XO 0 "register_operand")
- (unspec:XO [(match_operand:XO 1 "register_operand")]
- MMA_ACC))]
- "TARGET_MMA"
-{
- if (TARGET_DENSE_MATH)
- {
- if (!rtx_equal_p (operands[0], operands[1]))
- emit_move_insn (operands[0], operands[1]);
- DONE;
- }
-
- /* Generate the prime/de-prime code. */
-})
-
-(define_insn "*mma_<acc>"
+(define_insn "mma_<acc>"
[(set (match_operand:XO 0 "fpr_reg_operand" "=&d")
(unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0")]
MMA_ACC))]
- "TARGET_MMA && !TARGET_DENSE_MATH"
+ "TARGET_MMA"
"<acc> %A0"
[(set_attr "type" "mma")])
;; We can't have integer constants in XOmode so we wrap this in an
-;; UNSPEC_VOLATILE for the non-dense math case. For dense math, we don't need
-;; to disable optimization and we can do a normal UNSPEC.
+;; UNSPEC_VOLATILE.
-(define_expand "mma_xxsetaccz"
- [(set (match_operand:XO 0 "register_operand")
- (unspec_volatile:XO [(const_int 0)]
- UNSPECV_MMA_XXSETACCZ))]
- "TARGET_MMA"
-{
- if (TARGET_DENSE_MATH)
- {
- emit_insn (gen_mma_xxsetaccz_dm (operands[0]));
- DONE;
- }
-})
-
-(define_insn "*mma_xxsetaccz_vsx"
+(define_insn "mma_xxsetaccz"
[(set (match_operand:XO 0 "fpr_reg_operand" "=d")
(unspec_volatile:XO [(const_int 0)]
UNSPECV_MMA_XXSETACCZ))]
- "TARGET_MMA && !TARGET_DENSE_MATH"
+ "TARGET_MMA"
"xxsetaccz %A0"
[(set_attr "type" "mma")])
-
-(define_insn "mma_xxsetaccz_dm"
- [(set (match_operand:XO 0 "dmr_operand" "=wD")
- (unspec:XO [(const_int 0)]
- UNSPECV_MMA_XXSETACCZ))]
- "TARGET_DENSE_MATH"
- "dmsetdmrz %0"
- [(set_attr "type" "mma")])
-
(define_insn "mma_<vv>"
- [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d")
- (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "wa,v,?wa")
- (match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa")]
+ [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+ (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
+ (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")]
MMA_VV))]
"TARGET_MMA"
"<vv> %A0,%x1,%x2"
- [(set_attr "type" "mma")
- (set_attr "isa" "dm,not_dm,not_dm")])
+ [(set_attr "type" "mma")])
(define_insn "mma_<avv>"
- [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d")
- (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0,0")
- (match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa")
- (match_operand:V16QI 3 "vsx_register_operand" "wa,v,?wa")]
+ [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+ (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
+ (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
+ (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")]
MMA_AVV))]
"TARGET_MMA"
"<avv> %A0,%x2,%x3"
- [(set_attr "type" "mma")
- (set_attr "isa" "dm,not_dm,not_dm")])
+ [(set_attr "type" "mma")])
(define_insn "mma_<pv>"
- [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d")
- (unspec:XO [(match_operand:OO 1 "vsx_register_operand" "wa,v,?wa")
- (match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa")]
+ [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+ (unspec:XO [(match_operand:OO 1 "vsx_register_operand" "v,?wa")
+ (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")]
MMA_PV))]
"TARGET_MMA"
"<pv> %A0,%x1,%x2"
- [(set_attr "type" "mma")
- (set_attr "isa" "dm,not_dm,not_dm")])
+ [(set_attr "type" "mma")])
(define_insn "mma_<apv>"
- [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d")
- (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0,0")
- (match_operand:OO 2 "vsx_register_operand" "wa,v,?wa")
- (match_operand:V16QI 3 "vsx_register_operand" "wa,v,?wa")]
+ [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+ (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
+ (match_operand:OO 2 "vsx_register_operand" "v,?wa")
+ (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")]
MMA_APV))]
"TARGET_MMA"
"<apv> %A0,%x2,%x3"
- [(set_attr "type" "mma")
- (set_attr "isa" "dm,not_dm,not_dm")])
+ [(set_attr "type" "mma")])
(define_insn "mma_<vvi4i4i8>"
- [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d")
- (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "wa,v,?wa")
- (match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa")
- (match_operand:SI 3 "const_0_to_15_operand" "n,n,n")
- (match_operand:SI 4 "const_0_to_15_operand" "n,n,n")
- (match_operand:SI 5 "u8bit_cint_operand" "n,n,n")]
+ [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+ (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
+ (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
+ (match_operand:SI 3 "const_0_to_15_operand" "n,n")
+ (match_operand:SI 4 "const_0_to_15_operand" "n,n")
+ (match_operand:SI 5 "u8bit_cint_operand" "n,n")]
MMA_VVI4I4I8))]
"TARGET_MMA"
"<vvi4i4i8> %A0,%x1,%x2,%3,%4,%5"
[(set_attr "type" "mma")
- (set_attr "prefixed" "yes")
- (set_attr "isa" "dm,not_dm,not_dm")])
+ (set_attr "prefixed" "yes")])
(define_insn "mma_<avvi4i4i8>"
- [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d")
- (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0,0")
- (match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa")
- (match_operand:V16QI 3 "vsx_register_operand" "wa,v,?wa")
- (match_operand:SI 4 "const_0_to_15_operand" "n,n,n")
- (match_operand:SI 5 "const_0_to_15_operand" "n,n,n")
- (match_operand:SI 6 "u8bit_cint_operand" "n,n,n")]
+ [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+ (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
+ (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
+ (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")
+ (match_operand:SI 4 "const_0_to_15_operand" "n,n")
+ (match_operand:SI 5 "const_0_to_15_operand" "n,n")
+ (match_operand:SI 6 "u8bit_cint_operand" "n,n")]
MMA_AVVI4I4I8))]
"TARGET_MMA"
"<avvi4i4i8> %A0,%x2,%x3,%4,%5,%6"
[(set_attr "type" "mma")
- (set_attr "prefixed" "yes")
- (set_attr "isa" "dm,not_dm,not_dm")])
+ (set_attr "prefixed" "yes")])
(define_insn "mma_<vvi4i4i2>"
- [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d")
- (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "wa,v,?wa")
- (match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa")
- (match_operand:SI 3 "const_0_to_15_operand" "n,n,n")
- (match_operand:SI 4 "const_0_to_15_operand" "n,n,n")
- (match_operand:SI 5 "const_0_to_3_operand" "n,n,n")]
+ [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+ (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
+ (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
+ (match_operand:SI 3 "const_0_to_15_operand" "n,n")
+ (match_operand:SI 4 "const_0_to_15_operand" "n,n")
+ (match_operand:SI 5 "const_0_to_3_operand" "n,n")]
MMA_VVI4I4I2))]
"TARGET_MMA"
"<vvi4i4i2> %A0,%x1,%x2,%3,%4,%5"
[(set_attr "type" "mma")
- (set_attr "prefixed" "yes")
- (set_attr "isa" "dm,not_dm,not_dm")])
+ (set_attr "prefixed" "yes")])
(define_insn "mma_<avvi4i4i2>"
- [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d")
- (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0,0")
- (match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa")
- (match_operand:V16QI 3 "vsx_register_operand" "wa,v,?wa")
- (match_operand:SI 4 "const_0_to_15_operand" "n,n,n")
- (match_operand:SI 5 "const_0_to_15_operand" "n,n,n")
- (match_operand:SI 6 "const_0_to_3_operand" "n,n,n")]
+ [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+ (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
+ (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
+ (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")
+ (match_operand:SI 4 "const_0_to_15_operand" "n,n")
+ (match_operand:SI 5 "const_0_to_15_operand" "n,n")
+ (match_operand:SI 6 "const_0_to_3_operand" "n,n")]
MMA_AVVI4I4I2))]
"TARGET_MMA"
"<avvi4i4i2> %A0,%x2,%x3,%4,%5,%6"
[(set_attr "type" "mma")
- (set_attr "prefixed" "yes")
- (set_attr "isa" "dm,not_dm,not_dm")])
+ (set_attr "prefixed" "yes")])
(define_insn "mma_<vvi4i4>"
- [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d")
- (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "wa,v,?wa")
- (match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa")
- (match_operand:SI 3 "const_0_to_15_operand" "n,n,n")
- (match_operand:SI 4 "const_0_to_15_operand" "n,n,n")]
+ [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+ (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
+ (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
+ (match_operand:SI 3 "const_0_to_15_operand" "n,n")
+ (match_operand:SI 4 "const_0_to_15_operand" "n,n")]
MMA_VVI4I4))]
"TARGET_MMA"
"<vvi4i4> %A0,%x1,%x2,%3,%4"
[(set_attr "type" "mma")
- (set_attr "prefixed" "yes")
- (set_attr "isa" "dm,not_dm,not_dm")])
+ (set_attr "prefixed" "yes")])
(define_insn "mma_<avvi4i4>"
- [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d")
- (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0,0")
- (match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa")
- (match_operand:V16QI 3 "vsx_register_operand" "wa,v,?wa")
- (match_operand:SI 4 "const_0_to_15_operand" "n,n,n")
- (match_operand:SI 5 "const_0_to_15_operand" "n,n,n")]
+ [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+ (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
+ (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
+ (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")
+ (match_operand:SI 4 "const_0_to_15_operand" "n,n")
+ (match_operand:SI 5 "const_0_to_15_operand" "n,n")]
MMA_AVVI4I4))]
"TARGET_MMA"
"<avvi4i4> %A0,%x2,%x3,%4,%5"
[(set_attr "type" "mma")
- (set_attr "prefixed" "yes")
- (set_attr "isa" "dm,not_dm,not_dm")])
+ (set_attr "prefixed" "yes")])
(define_insn "mma_<pvi4i2>"
- [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d")
- (unspec:XO [(match_operand:OO 1 "vsx_register_operand" "wa,v,?wa")
- (match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa")
- (match_operand:SI 3 "const_0_to_15_operand" "n,n,n")
- (match_operand:SI 4 "const_0_to_3_operand" "n,n,n")]
+ [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+ (unspec:XO [(match_operand:OO 1 "vsx_register_operand" "v,?wa")
+ (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
+ (match_operand:SI 3 "const_0_to_15_operand" "n,n")
+ (match_operand:SI 4 "const_0_to_3_operand" "n,n")]
MMA_PVI4I2))]
"TARGET_MMA"
"<pvi4i2> %A0,%x1,%x2,%3,%4"
[(set_attr "type" "mma")
- (set_attr "prefixed" "yes")
- (set_attr "isa" "dm,not_dm,not_dm")])
+ (set_attr "prefixed" "yes")])
(define_insn "mma_<apvi4i2>"
- [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d")
- (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0,0")
- (match_operand:OO 2 "vsx_register_operand" "wa,v,?wa")
- (match_operand:V16QI 3 "vsx_register_operand" "wa,v,?wa")
- (match_operand:SI 4 "const_0_to_15_operand" "n,n,n")
- (match_operand:SI 5 "const_0_to_3_operand" "n,n,n")]
+ [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+ (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
+ (match_operand:OO 2 "vsx_register_operand" "v,?wa")
+ (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")
+ (match_operand:SI 4 "const_0_to_15_operand" "n,n")
+ (match_operand:SI 5 "const_0_to_3_operand" "n,n")]
MMA_APVI4I2))]
"TARGET_MMA"
"<apvi4i2> %A0,%x2,%x3,%4,%5"
[(set_attr "type" "mma")
- (set_attr "prefixed" "yes")
- (set_attr "isa" "dm,not_dm,not_dm")])
+ (set_attr "prefixed" "yes")])
(define_insn "mma_<vvi4i4i4>"
- [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d")
- (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "wa,v,?wa")
- (match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa")
- (match_operand:SI 3 "const_0_to_15_operand" "n,n,n")
- (match_operand:SI 4 "const_0_to_15_operand" "n,n,n")
- (match_operand:SI 5 "const_0_to_15_operand" "n,n,n")]
+ [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+ (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
+ (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
+ (match_operand:SI 3 "const_0_to_15_operand" "n,n")
+ (match_operand:SI 4 "const_0_to_15_operand" "n,n")
+ (match_operand:SI 5 "const_0_to_15_operand" "n,n")]
MMA_VVI4I4I4))]
"TARGET_MMA"
"<vvi4i4i4> %A0,%x1,%x2,%3,%4,%5"
[(set_attr "type" "mma")
- (set_attr "prefixed" "yes")
- (set_attr "isa" "dm,not_dm,not_dm")])
+ (set_attr "prefixed" "yes")])
(define_insn "mma_<avvi4i4i4>"
- [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d")
- (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0,0")
- (match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa")
- (match_operand:V16QI 3 "vsx_register_operand" "wa,v,?wa")
- (match_operand:SI 4 "const_0_to_15_operand" "n,n,n")
- (match_operand:SI 5 "const_0_to_15_operand" "n,n,n")
- (match_operand:SI 6 "const_0_to_15_operand" "n,n,n")]
+ [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+ (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
+ (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
+ (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")
+ (match_operand:SI 4 "const_0_to_15_operand" "n,n")
+ (match_operand:SI 5 "const_0_to_15_operand" "n,n")
+ (match_operand:SI 6 "const_0_to_15_operand" "n,n")]
MMA_AVVI4I4I4))]
"TARGET_MMA"
"<avvi4i4i4> %A0,%x2,%x3,%4,%5,%6"
[(set_attr "type" "mma")
- (set_attr "prefixed" "yes")
- (set_attr "isa" "dm,not_dm,not_dm")])
+ (set_attr "prefixed" "yes")])
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index baf1f4dc92b..2803014f2b6 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -600,9 +600,6 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags)
/* Tell the user if we support the MMA instructions. */
if ((flags & OPTION_MASK_MMA) != 0)
rs6000_define_or_undefine_macro (define_p, "__MMA__");
- /* Tell the user if we support the dense math instructions. */
- if ((flags & OPTION_MASK_DENSE_MATH) != 0)
- rs6000_define_or_undefine_macro (define_p, "__PPC_DMR__");
/* Whether pc-relative code is being generated. */
if ((flags & OPTION_MASK_PCREL) != 0)
rs6000_define_or_undefine_macro (define_p, "__PCREL__");
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index c64d4e2cf2b..8685e2a1275 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -13955,13 +13955,8 @@ print_operand (FILE *file, rtx x, int code)
overlapping with the FPR registers. */
if (!REG_P (x))
output_operand_lossage ("invalid %%A value");
- else if (TARGET_DENSE_MATH)
- {
- if (DMR_REGNO_P (REGNO (x)))
- fprintf (file, "%d", REGNO (x) - FIRST_DMR_REGNO);
- else
- output_operand_lossage ("%%A operand is not a DMR");
- }
+ else if (TARGET_DENSE_MATH && DMR_REGNO_P (REGNO (x)))
+ fprintf (file, "%d", REGNO (x) - FIRST_DMR_REGNO);
else if (!FP_REGNO_P (REGNO (x)) || (REGNO (x) % 4) != 0)
output_operand_lossage ("invalid %%A value");
else
@@ -27405,7 +27400,7 @@ rs6000_split_multireg_move (rtx dst, rtx src)
/* If we are reading an accumulator register, we have to
deprime it before we can access it. */
- if (TARGET_MMA && !TARGET_DENSE_MATH
+ if (TARGET_MMA
&& GET_MODE (src) == XOmode && FP_REGNO_P (REGNO (src)))
emit_insn (gen_mma_xxmfacc (src, src));
@@ -27437,9 +27432,9 @@ rs6000_split_multireg_move (rtx dst, rtx src)
emit_insn (gen_rtx_SET (dst2, src2));
}
- /* If we are writing an accumulator register that overlaps with the
- FPR registers, we have to prime it after we've written it. */
- if (TARGET_MMA && !TARGET_DENSE_MATH
+ /* If we are writing an accumulator register, we have to
+ prime it after we've written it. */
+ if (TARGET_MMA
&& GET_MODE (dst) == XOmode && FP_REGNO_P (REGNO (dst)))
emit_insn (gen_mma_xxmtacc (dst, dst));
@@ -27508,9 +27503,9 @@ rs6000_split_multireg_move (rtx dst, rtx src)
emit_insn (gen_rtx_SET (dst_i, op));
}
- /* On systems without dense math where accumulators overlap with the
- vector registers, we have to prime it after we've written it. */
- if (GET_MODE (src) == XOmode && !TARGET_DENSE_MATH)
+ /* We are writing an accumulator register, so we have to
+ prime it after we've written it. */
+ if (GET_MODE (src) == XOmode)
emit_insn (gen_mma_xxmtacc (dst, dst));
return;
@@ -27521,9 +27516,9 @@ rs6000_split_multireg_move (rtx dst, rtx src)
if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
{
- /* If we are reading an accumulator register and we don't have dense
- math, we have to deprime it before we can access it. */
- if (TARGET_MMA && !TARGET_DENSE_MATH
+ /* If we are reading an accumulator register, we have to
+ deprime it before we can access it. */
+ if (TARGET_MMA
&& GET_MODE (src) == XOmode && FP_REGNO_P (REGNO (src)))
emit_insn (gen_mma_xxmfacc (src, src));
@@ -27551,7 +27546,7 @@ rs6000_split_multireg_move (rtx dst, rtx src)
/* If we are writing an accumulator register, we have to
prime it after we've written it. */
- if (TARGET_MMA && !TARGET_DENSE_MATH
+ if (TARGET_MMA
&& GET_MODE (dst) == XOmode && FP_REGNO_P (REGNO (dst)))
emit_insn (gen_mma_xxmtacc (dst, dst));
}
@@ -27688,7 +27683,7 @@ rs6000_split_multireg_move (rtx dst, rtx src)
/* If we are reading an accumulator register, we have to
deprime it before we can access it. */
- if (TARGET_MMA && !TARGET_DENSE_MATH && REG_P (src)
+ if (TARGET_MMA && REG_P (src)
&& GET_MODE (src) == XOmode && FP_REGNO_P (REGNO (src)))
emit_insn (gen_mma_xxmfacc (src, src));
@@ -27720,7 +27715,7 @@ rs6000_split_multireg_move (rtx dst, rtx src)
/* If we are writing an accumulator register, we have to
prime it after we've written it. */
- if (TARGET_MMA && !TARGET_DENSE_MATH && REG_P (dst)
+ if (TARGET_MMA && REG_P (dst)
&& GET_MODE (dst) == XOmode && FP_REGNO_P (REGNO (dst)))
emit_insn (gen_mma_xxmtacc (dst, dst));
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