[gcc r14-6577] RISC-V: Remove xfail for some of the SLP tests

[Pan Li]

https://gcc.gnu.org/g:7304e85ffff8cd832bb520f2b4f341fca286d510

commit r14-6577-g7304e85ffff8cd832bb520f2b4f341fca286d510
Author: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date:   Fri Dec 15 16:06:10 2023 +0800

    RISC-V: Remove xfail for some of the SLP tests
    
    Due to recent middle-end cost model changes, now we can do more VLA SLP.
    
    Fix these following regressions:
    
    XPASS: gcc.target/riscv/rvv/autovec/partial/slp-1.c scan-assembler \\tvand
    XPASS: gcc.target/riscv/rvv/autovec/partial/slp-1.c scan-assembler \\tvand
    XPASS: gcc.target/riscv/rvv/autovec/partial/slp-1.c scan-assembler \\tvid\\.v
    XPASS: gcc.target/riscv/rvv/autovec/partial/slp-1.c scan-assembler \\tvid\\.v
    XPASS: gcc.target/riscv/rvv/autovec/partial/slp-1.c scan-tree-dump-times optimized ".VEC_PERM" 1
    XPASS: gcc.target/riscv/rvv/autovec/partial/slp-1.c scan-tree-dump-times optimized ".VEC_PERM" 1
    XPASS: gcc.target/riscv/rvv/autovec/partial/slp-16.c scan-assembler \\tvid\\.v
    XPASS: gcc.target/riscv/rvv/autovec/partial/slp-16.c scan-assembler \\tvid\\.v
    XPASS: gcc.target/riscv/rvv/autovec/partial/slp-16.c scan-tree-dump-times optimized ".VEC_PERM" 1
    XPASS: gcc.target/riscv/rvv/autovec/partial/slp-16.c scan-tree-dump-times optimized ".VEC_PERM" 1
    XPASS: gcc.target/riscv/rvv/autovec/partial/slp-3.c scan-tree-dump-times optimized ".VEC_PERM" 1
    XPASS: gcc.target/riscv/rvv/autovec/partial/slp-3.c scan-tree-dump-times optimized ".VEC_PERM" 1
    XPASS: gcc.target/riscv/rvv/autovec/partial/slp-5.c scan-tree-dump-times optimized ".VEC_PERM" 1
    XPASS: gcc.target/riscv/rvv/autovec/partial/slp-5.c scan-tree-dump-times optimized ".VEC_PERM" 1
    
    Committed.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/rvv/autovec/partial/slp-1.c: Remove xfail of M2.
            * gcc.target/riscv/rvv/autovec/partial/slp-16.c: Ditto.
            * gcc.target/riscv/rvv/autovec/partial/slp-3.c: Ditto.
            * gcc.target/riscv/rvv/autovec/partial/slp-5.c: Ditto.

Diff:
---
 gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c  | 8 ++++----
 gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c | 6 +++---
 gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c  | 4 ++--
 gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c  | 4 ++--
 4 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c
index 34622ce9aff..948b20b68d3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c
@@ -20,7 +20,7 @@ f (int8_t *restrict a, int8_t *restrict b, int n)
 }
 
 /* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen
-   instead of SLP when riscv-autovec-lmul=m1 or m2.  */
-/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" "--param riscv-autovec-lmul=m8" } } } } */
-/* { dg-final { scan-assembler {\tvid\.v} { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" } } } } */
-/* { dg-final { scan-assembler {\tvand} { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" } } } } */
+   instead of SLP when riscv-autovec-lmul=m1.  */
+/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m8" } } } } */
+/* { dg-final { scan-assembler {\tvid\.v} { xfail { any-opts "--param riscv-autovec-lmul=m1" } } } } */
+/* { dg-final { scan-assembler {\tvand} { xfail { any-opts "--param riscv-autovec-lmul=m1" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c
index 80c77ef679a..7b23cafab3f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c
@@ -20,7 +20,7 @@ f (uint8_t *restrict a, uint8_t *restrict b, int n)
 }
 
 /* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen
-   instead of SLP when riscv-autovec-lmul=m1 or m2.  */
-/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" "--param riscv-autovec-lmul=m8" } } } } */
-/* { dg-final { scan-assembler {\tvid\.v} { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" } } } } */
+   instead of SLP when riscv-autovec-lmul=m1.  */
+/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m8" } } } } */
+/* { dg-final { scan-assembler {\tvid\.v} { xfail { any-opts "--param riscv-autovec-lmul=m1"} } } } */
 /* { dg-final { scan-assembler-not {\tvmul} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c
index 75298bd7525..3622c59c439 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c
@@ -20,5 +20,5 @@ f (int8_t *restrict a, int8_t *restrict b, int n)
 }
 
 /* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen
-   instead of SLP when riscv-autovec-lmul=m1 or m2.  */
-/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" "--param riscv-autovec-lmul=m8" } } } } */
+   instead of SLP when riscv-autovec-lmul=m1.  */
+/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m8" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c
index c1b31a430f2..5c0a6775474 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c
@@ -20,5 +20,5 @@ f (int8_t *restrict a, int8_t *restrict b, int n)
 }
 
 /* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen
-   instead of SLP when riscv-autovec-lmul=m1 or m2.  */
-/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" "--param riscv-autovec-lmul=m8" } } } } */
+   instead of SLP when riscv-autovec-lmul=m1.  */
+/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m8" } } } } */