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r278343 - in /trunk/gcc: ChangeLog config/aarch...
- From: rsandifo at gcc dot gnu dot org
- To: gcc-cvs at gcc dot gnu dot org
- Date: Sat, 16 Nov 2019 11:11:47 -0000
- Subject: r278343 - in /trunk/gcc: ChangeLog config/aarch...
Author: rsandifo
Date: Sat Nov 16 11:11:47 2019
New Revision: 278343
URL: https://gcc.gnu.org/viewcvs?rev=278343&root=gcc&view=rev
Log:
[AArch64] Pattern-match SVE extending loads
This patch pattern-matches a partial SVE load followed by a sign or zero
extension into an extending load. (The partial load is already an
extending load; we just don't rely on the upper bits of the elements.)
Nothing yet uses the extra LDFF1 and LDNF1 combinations, but it seemed
more consistent to provide them, since I needed to update the pattern
to use a predicated extension anyway.
2019-11-16 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-sve.md
(@aarch64_load_<ANY_EXTEND:optab><VNx8_WIDE:mode><VNx8_NARROW:mode>):
(@aarch64_load_<ANY_EXTEND:optab><VNx4_WIDE:mode><VNx4_NARROW:mode>)
(@aarch64_load_<ANY_EXTEND:optab><VNx2_WIDE:mode><VNx2_NARROW:mode>):
Combine into...
(@aarch64_load_<ANY_EXTEND:optab><SVE_HSDI:mode><SVE_PARTIAL_I:mode>):
...this new pattern, handling extension to partial modes as well
as full modes. Describe the extension as a predicated rather than
unpredicated extension.
(@aarch64_ld<fn>f1_<ANY_EXTEND:optab><VNx8_WIDE:mode><VNx8_NARROW:mode>)
(@aarch64_ld<fn>f1_<ANY_EXTEND:optab><VNx4_WIDE:mode><VNx4_NARROW:mode>)
(@aarch64_ld<fn>f1_<ANY_EXTEND:optab><VNx2_WIDE:mode><VNx2_NARROW:mode>):
Combine into...
(@aarch64_ld<fn>f1_<ANY_EXTEND:optab><SVE_HSDI:mode><SVE_PARTIAL_I:mode>):
...this new pattern, handling extension to partial modes as well
as full modes. Describe the extension as a predicated rather than
unpredicated extension.
* config/aarch64/aarch64-sve-builtins.cc
(function_expander::use_contiguous_load_insn): Add an extra
predicate for extending loads.
* config/aarch64/aarch64.c (aarch64_extending_load_p): New function.
(aarch64_sve_adjust_stmt_cost): Likewise.
(aarch64_add_stmt_cost): Use aarch64_sve_adjust_stmt_cost to adjust
the cost of SVE vector stmts.
gcc/testsuite/
* gcc.target/aarch64/sve/load_extend_1.c: New test.
* gcc.target/aarch64/sve/load_extend_2.c: Likewise.
* gcc.target/aarch64/sve/load_extend_3.c: Likewise.
* gcc.target/aarch64/sve/load_extend_4.c: Likewise.
* gcc.target/aarch64/sve/load_extend_5.c: Likewise.
* gcc.target/aarch64/sve/load_extend_6.c: Likewise.
* gcc.target/aarch64/sve/load_extend_7.c: Likewise.
* gcc.target/aarch64/sve/load_extend_8.c: Likewise.
* gcc.target/aarch64/sve/load_extend_9.c: Likewise.
* gcc.target/aarch64/sve/load_extend_10.c: Likewise.
* gcc.target/aarch64/sve/reduc_4.c: Add
--param aarch64-sve-compare-costs=0.
Added:
trunk/gcc/testsuite/gcc.target/aarch64/sve/load_extend_1.c
trunk/gcc/testsuite/gcc.target/aarch64/sve/load_extend_10.c
trunk/gcc/testsuite/gcc.target/aarch64/sve/load_extend_2.c
trunk/gcc/testsuite/gcc.target/aarch64/sve/load_extend_3.c
trunk/gcc/testsuite/gcc.target/aarch64/sve/load_extend_4.c
trunk/gcc/testsuite/gcc.target/aarch64/sve/load_extend_5.c
trunk/gcc/testsuite/gcc.target/aarch64/sve/load_extend_6.c
trunk/gcc/testsuite/gcc.target/aarch64/sve/load_extend_7.c
trunk/gcc/testsuite/gcc.target/aarch64/sve/load_extend_8.c
trunk/gcc/testsuite/gcc.target/aarch64/sve/load_extend_9.c
Modified:
trunk/gcc/ChangeLog
trunk/gcc/config/aarch64/aarch64-sve-builtins.cc
trunk/gcc/config/aarch64/aarch64-sve.md
trunk/gcc/config/aarch64/aarch64.c
trunk/gcc/testsuite/ChangeLog
trunk/gcc/testsuite/gcc.target/aarch64/sve/reduc_4.c