gcc/gcc ChangeLog config/arm/arm-modes.def con ...

[rearnsha at gcc dot gnu dot org]

CVSROOT:	/cvs/gcc
Module name:	gcc
Changes by:	rearnsha@gcc.gnu.org	2003-10-17 10:58:17

Modified files:
	gcc            : ChangeLog 
	gcc/config/arm : arm-modes.def arm-protos.h arm.c arm.h arm.md 

Log message:
	* arm-modes.def (CC_Nmode): New condition code mode.
	* arm.c (thumb_condition_code): Delete.
	(arm_select_cc_mode): Handle single-bit test for Thumb.
	(arm_print_operand, cases 'd' and 'D'): Don't special case the
	condition code logic for Thumb.
	(get_arm_condition_code): Handle CC_Nmode.
	(thumb_cbrch_target_operand): New function.
	* arm.h (PREDICATE_CODES): Add thumb_cbrch_target_operand.
	* arm-protos.h (thumb_cbrch_target_operand): Add prototype.
	* arm.md: Add Thumb split patterns for zero_extract and
	sign_extract.
	(tbit_cbranch, andsi3_cbranch_scratch, andsi3_cbranch)
	(orrsi3_cbranch_scratch, orrsi3_cbranch, xorsi3_cbranch_scratch)
	(xorsi3_cbranch, addsi3_cbranch, addsi3_cbranch_scratch)
	(subsi3_cbranch, subsi3_cbranch_scratch): New Thumb patterns.
	(cbranchne_decr1): Re-work to use CC_Nmode.
	
	* arm.c (thumb_expand_epilogue): Add clobbers of registers restored
	by the return instruction.  Add a use of the link register if it
	wasn't stored.

Patches:
http://gcc.gnu.org/cgi-bin/cvsweb.cgi/gcc/gcc/ChangeLog.diff?cvsroot=gcc&r1=2.1440&r2=2.1441
http://gcc.gnu.org/cgi-bin/cvsweb.cgi/gcc/gcc/config/arm/arm-modes.def.diff?cvsroot=gcc&r1=1.3&r2=1.4
http://gcc.gnu.org/cgi-bin/cvsweb.cgi/gcc/gcc/config/arm/arm-protos.h.diff?cvsroot=gcc&r1=1.59&r2=1.60
http://gcc.gnu.org/cgi-bin/cvsweb.cgi/gcc/gcc/config/arm/arm.c.diff?cvsroot=gcc&r1=1.296&r2=1.297
http://gcc.gnu.org/cgi-bin/cvsweb.cgi/gcc/gcc/config/arm/arm.h.diff?cvsroot=gcc&r1=1.206&r2=1.207
http://gcc.gnu.org/cgi-bin/cvsweb.cgi/gcc/gcc/config/arm/arm.md.diff?cvsroot=gcc&r1=1.143&r2=1.144