[Bug target/84710] [8 Regression] ICE: RTL check: expected code 'reg', have 'subreg' in rhs_regno, at rtl.h:1896 with -O -fno-forward-propagate

["jakub at gcc dot gnu.org" <gcc-bugzilla at gcc dot gnu dot org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84710

--- Comment #5 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
(In reply to Segher Boessenkool from comment #4)
> The testcase does not crash for me; does it need more non-default options?
> 
> The testcase has UB of course (d is undefined).

The compiler needs to be configured with --enable-checking=yes,rtl .

--- gcc/combine.c.jj    2018-03-05 23:13:26.478215559 +0100
+++ gcc/combine.c       2018-03-06 08:50:17.756288841 +0100
@@ -4283,12 +4283,8 @@ try_combine (rtx_insn *i3, rtx_insn *i2,
       if (GET_CODE (x) == PARALLEL)
        x = XVECEXP (newi2pat, 0, 0);

-      /* It can only be a SET of a REG or of a paradoxical SUBREG of a REG. 
*/
-      x = SET_DEST (x);
-      if (paradoxical_subreg_p (x))
-       x = SUBREG_REG (x);
-
-      unsigned int regno = REGNO (x);
+      /* It can only be a SET of a REG or of a SUBREG of a REG.  */
+      unsigned int regno = reg_or_subregno (SET_DEST (x));

       bool done = false;
       for (rtx_insn *insn = NEXT_INSN (i3);

is the combine.c part I'll be testing.  And, the testcase is dg-do compile
only,
so it doesn't matter if there is UB in it or not, we shouldn't ICE on it (and
yes, my attempts to get rid of the uninit use just resulted in the ICE no
longer happening).