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[Bug rtl-optimization/84071] [7/8 regression] wrong elimination of zero-extension after sign-extended load
- From: "ebotcazou at gcc dot gnu.org" <gcc-bugzilla at gcc dot gnu dot org>
- To: gcc-bugs at gcc dot gnu dot org
- Date: Fri, 02 Feb 2018 17:25:56 +0000
- Subject: [Bug rtl-optimization/84071] [7/8 regression] wrong elimination of zero-extension after sign-extended load
- Auto-submitted: auto-generated
- References: <bug-84071-4@http.gcc.gnu.org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84071
--- Comment #22 from Eric Botcazou <ebotcazou at gcc dot gnu.org> ---
> So MIPS fundamentally needs this feature to work correctly; whether AArch64
> needs it or may just benefit from it depends on a lot of detailed knowledge
> of the ISA and architecture. Given Richard Sandiford is currently working on
> ARM ports but also fully understands the MIPS arch then he may be a good
> person to consult.
If "this feature" is WORD_REGISTER_OPERATIONS, then I don't think that any
target, including MIPS, really needs it. Defining the macro is only an
optimization and a way to convey multiple properties of the target with only
one setting. And, for MIPS, the implementation of the sign-extension invariant
is done by other means.